reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10955 return DAG.getUNDEF(VT); 10963 if (VT.isVector() && 10965 (!LegalOperations && VT.isInteger() && N0.getValueType().isInteger() && 10966 TLI.isTypeLegal(VT.getVectorElementType()))) && 10970 VT.getVectorElementType()); 10978 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() && 10978 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() && 10979 TLI.isOperationLegal(ISD::ConstantFP, VT)) || 10980 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() && 10980 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() && 10981 TLI.isOperationLegal(ISD::Constant, VT))) { 10982 SDValue C = DAG.getBitcast(VT, N0); 10990 return DAG.getBitcast(VT, N0.getOperand(0)); 10997 TLI.hasBigEndianPartOrdering(VT, DAG.getDataLayout()) && 11004 TLI.isOperationLegal(ISD::LOAD, VT))) { 11007 if (TLI.isLoadBitCastBeneficial(N0.getValueType(), VT, DAG, 11010 DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), 11035 N0.getNode()->hasOneUse() && VT.isInteger() && 11036 !VT.isVector() && !N0.getValueType().isVector()) { 11037 SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0)); 11042 assert(VT.getSizeInBits() == 128); 11044 APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64); 11060 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); 11062 return DAG.getNode(ISD::XOR, DL, VT, NewConv, FlipBits); 11064 APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); 11066 return DAG.getNode(ISD::XOR, DL, VT, 11067 NewConv, DAG.getConstant(SignBit, DL, VT)); 11069 return DAG.getNode(ISD::AND, DL, VT, 11070 NewConv, DAG.getConstant(~SignBit, DL, VT)); 11086 VT.isInteger() && !VT.isVector()) { 11086 VT.isInteger() && !VT.isVector()) { 11094 unsigned VTWidth = VT.getSizeInBits(); 11096 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X); 11107 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); 11112 APInt SignBit = APInt::getSignMask(VT.getSizeInBits() / 2); 11113 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); 11115 SDValue X = DAG.getBitcast(VT, N0.getOperand(1)); 11117 SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X); 11129 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); 11131 return DAG.getNode(ISD::XOR, SDLoc(N), VT, Cst, FlipBits); 11133 APInt SignBit = APInt::getSignMask(VT.getSizeInBits()); 11134 X = DAG.getNode(ISD::AND, SDLoc(X), VT, 11135 X, DAG.getConstant(SignBit, SDLoc(X), VT)); 11138 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0)); 11139 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT, 11140 Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT)); 11143 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst); 11149 if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT)) 11156 if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() && 11156 if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() && 11158 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() && 11159 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) { 11166 Op.getOperand(0).getValueType() == VT) 11170 return DAG.getBitcast(VT, Op); 11183 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements(); 11190 TLI.buildLegalVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask, DAG);