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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 2860 if (VT.isVector()) {
2872 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
2876 return DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2887 return DAG.getNode(ISD::ADD, DL, VT, N0,
2888 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
2892 unsigned BitWidth = VT.getScalarSizeInBits();
2901 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
2902 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
2923 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
2927 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
2946 ISD::SUB, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
2948 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
2956 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2959 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
2968 ISD::ADD, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
2970 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
2978 ISD::SUB, DL, VT, N0.getOperand(0).getNode(), N1.getNode());
2980 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
2988 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
2994 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
3000 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
3005 return DAG.getNode(ISD::ADD, DL, VT, N0,
3006 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
3013 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3016 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3020 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3023 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3044 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
3045 DAG.getAllOnesConstant(DL, VT));
3046 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
3053 if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) {
3054 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
3055 return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
3055 return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
3062 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3063 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
3068 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3069 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3075 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3076 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3081 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
3082 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3090 TLI.getBooleanContents(VT) ==
3092 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3093 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
3097 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3102 unsigned OpSizeInBits = VT.getScalarSizeInBits();
3105 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
3115 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
3122 DL, VT);
3129 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3130 DAG.getConstant(1, DL, VT));
3131 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
3142 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3143 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
3147 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
3151 SDValue Zero = DAG.getConstant(0, DL, VT);
3152 SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
3154 DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,