reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/TargetRegisterInfo.h

  741   unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;

References

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

  500   return TRI.getRegSizeInBits(Reg, MRI);

lib/CodeGen/MachineVerifier.cpp

 1556       unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
 1557       unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);

lib/Target/AArch64/AArch64FrameLowering.cpp

 2232     CSStackSize += TRI->getRegSizeInBits(Reg, MRI) / 8;

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1377   assert((TRI->getRegSizeInBits(Addr.Base.LoReg, *MRI) == 32 ||
 1381   assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 ||

lib/Target/AMDGPU/SILowerI1Copies.cpp

  105            TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) ==
  496   unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
  702         assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  425   if (TRI.getRegSizeInBits(Reg, MRI) != 32) {

lib/Target/ARM/ARMAsmPrinter.cpp

 1133             TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;

lib/Target/X86/X86CallLowering.cpp

  136         MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);
  270           MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI);