reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1638 assert(VT == MVT::i64 && "LowerUDIVREM64 expects an i64"); 1640 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext()); 1690 SDValue Rcp64 = DAG.getBitcast(VT, 1693 SDValue Zero64 = DAG.getConstant(0, DL, VT); 1694 SDValue One64 = DAG.getConstant(1, DL, VT); 1698 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); 1699 SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64); 1700 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); 1711 SDValue Add1 = DAG.getBitcast(VT, 1714 SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1); 1715 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); 1727 SDValue Add2 = DAG.getBitcast(VT, 1729 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); 1731 SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3); 1740 SDValue Sub1 = DAG.getBitcast(VT, 1761 SDValue Sub2 = DAG.getBitcast(VT, 1764 SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64); 1773 SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64); 1781 SDValue Sub3 = DAG.getBitcast(VT, 1819 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit); 1822 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); 1822 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT)); 1824 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit); 1832 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);