reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  289       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
  290       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
  293       MI = MCInst(); // clear
  295       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
  298       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
  301       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
  304       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
  312         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
  317         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
  326         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
  338     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
  341     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
  344     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
  347     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
  352     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
  355     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
  358     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
  361     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
  365         !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
  371   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
  372               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
  373               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
  374               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
  375               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
  376               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
  377               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
  379     insertNamedMCOperand(MI, MCOperand::createImm(0),
  383   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
  385         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
  387         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
  395           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
  395           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
  403       Res = convertMIMGInst(MI);
  407     Res = convertSDWAInst(MI);
  409   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
  412     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
  414     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
  415          !MI.getOperand(VDstIn_Idx).isReg() ||
  416          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
  416          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
  417       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
  418         MI.erase(&MI.getOperand(VDstIn_Idx));
  418         MI.erase(&MI.getOperand(VDstIn_Idx));
  419       insertNamedMCOperand(MI,
  420         MCOperand::createReg(MI.getOperand(Tied).getReg()),