reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
475 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 478 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 481 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 482 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 485 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 487 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 494 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 496 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 503 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 507 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 528 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 531 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 537 if (MI.getOperand(TFEIdx).getImm()) 554 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 570 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 581 MI.setOpcode(NewOpcode); 584 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 588 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 593 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 596 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 596 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 597 MI.begin() + VAddr0Idx + Info->VAddrDwords);