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References

lib/Target/AMDGPU/R600ISelLowering.cpp
 1251       SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain);
 1253       SDValue NewStore = DAG.getTruncStore(
 1260     return scalarizeVectorStore(StoreNode, DAG);
 1267     return expandUnalignedStore(StoreNode, DAG);
 1270   SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr,
 1271                                   DAG.getConstant(2, DL, PtrVT));
 1280         MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32);
 1284         MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32);
 1287       SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr,
 1288                                       DAG.getConstant(0x00000003, DL, PtrVT));
 1289       SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex,
 1290                                      DAG.getConstant(3, DL, VT));
 1293       SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift);
 1296       SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant);
 1297       SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift);
 1303         DAG.getConstant(0, DL, MVT::i32),
 1304         DAG.getConstant(0, DL, MVT::i32),
 1307       SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src);
 1309       return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL,
 1314       Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
 1319         Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());
 1330     return lowerPrivateTruncStore(StoreNode, DAG);
 1335     Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr);
 1336     return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand());