reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

   63 class R600InstrInfo;

lib/Target/AMDGPU/R600ISelLowering.h

   21 class R600InstrInfo;

lib/Target/AMDGPU/R600MachineScheduler.h

   24 class R600InstrInfo;

References

lib/Target/AMDGPU/AMDGPUSubtarget.h

 1211   R600InstrInfo InstrInfo;
 1229   const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }

lib/Target/AMDGPU/AMDILCFGStructurizer.cpp

  176   const R600InstrInfo *TII = nullptr;

lib/Target/AMDGPU/R600ClauseMergePass.cpp

   47   const R600InstrInfo *TII;

lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp

  235   const R600InstrInfo *TII = nullptr;

lib/Target/AMDGPU/R600EmitClauseMarkers.cpp

   49   const R600InstrInfo *TII = nullptr;

lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp

   41   const R600InstrInfo *TII = nullptr;

lib/Target/AMDGPU/R600ISelLowering.cpp

  295   const R600InstrInfo *TII = Subtarget->getInstrInfo();
 2085   const R600InstrInfo *TII = Subtarget->getInstrInfo();
 2215   const R600InstrInfo *TII = Subtarget->getInstrInfo();

lib/Target/AMDGPU/R600InstrInfo.cpp

  375         R600InstrInfo::BankSwizzle Swz) {
  379   case R600InstrInfo::ALU_VEC_012_SCL_210:
  381   case R600InstrInfo::ALU_VEC_021_SCL_122:
  384   case R600InstrInfo::ALU_VEC_102_SCL_221:
  387   case R600InstrInfo::ALU_VEC_120_SCL_212:
  391   case R600InstrInfo::ALU_VEC_201:
  395   case R600InstrInfo::ALU_VEC_210:
  402 static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
  405   case R600InstrInfo::ALU_VEC_012_SCL_210: {
  409   case R600InstrInfo::ALU_VEC_021_SCL_122: {
  413   case R600InstrInfo::ALU_VEC_120_SCL_212: {
  417   case R600InstrInfo::ALU_VEC_102_SCL_221: {
  431     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
  433     R600InstrInfo::BankSwizzle TransSwz) const {
  444         if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
  445             Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
  480     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
  484   while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
  487     SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
  500     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
  502     R600InstrInfo::BankSwizzle TransSwz) const {
  515 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
  561   static const R600InstrInfo::BankSwizzle TransSwz[] = {

lib/Target/AMDGPU/R600InstrInfo.h

  124     const std::vector<R600InstrInfo::BankSwizzle> &Swz,
  126     R600InstrInfo::BankSwizzle TransSwz) const;
  130     std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
  132     R600InstrInfo::BankSwizzle TransSwz) const;

lib/Target/AMDGPU/R600MachineScheduler.h

   29   const R600InstrInfo *TII = nullptr;

lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

   99   const R600InstrInfo *TII = nullptr;

lib/Target/AMDGPU/R600Packetizer.cpp

   57   const R600InstrInfo *TII;
  228                                  std::vector<R600InstrInfo::BankSwizzle> &BS,
  296     std::vector<R600InstrInfo::BankSwizzle> BS;
  327   const R600InstrInfo *TII = ST.getInstrInfo();

lib/Target/AMDGPU/R600RegisterInfo.cpp

   35   const R600InstrInfo *TII = ST.getInstrInfo();