|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 930 if (MI.modifiesRegister(AMDGPU::EXEC, TRI)) {
950 &MI, TII, MRI, TRI, CallAddrOpIdx, false);
961 &MI, TII, MRI, TRI, RtnAddrOpIdx, false);
991 ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I, false);
993 if (TRI->isVGPR(MRIA, Op.getReg())) {
1027 ScoreBrackets.getRegInterval(&MI, TII, MRI, TRI, I, true);
1029 if (TRI->isVGPR(MRIA, Def.getReg())) {
1206 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_ACCESS, Inst);
1207 ScoreBrackets->updateByEvent(TII, TRI, MRI, GDS_GPR_LOCK, Inst);
1209 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst);
1216 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst);
1219 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_READ_ACCESS, Inst);
1221 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_WRITE_ACCESS, Inst);
1225 ScoreBrackets->updateByEvent(TII, TRI, MRI, LDS_ACCESS, Inst);
1241 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_ACCESS, Inst);
1246 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_READ_ACCESS, Inst);
1248 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMEM_WRITE_ACCESS, Inst);
1252 ScoreBrackets->updateByEvent(TII, TRI, MRI, VMW_GPR_LOCK, Inst);
1255 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
1268 ScoreBrackets->updateByEvent(TII, TRI, MRI, SQ_MESSAGE, Inst);
1274 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_PARAM_ACCESS, Inst);
1276 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_POS_ACCESS, Inst);
1278 ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_GPR_LOCK, Inst);
1283 ScoreBrackets->updateByEvent(TII, TRI, MRI, SMEM_ACCESS, Inst);
1432 TRI->getVCC())
1433 .addReg(TRI->getVCC());
1447 TRI = &TII->getRegisterInfo();
1466 RegisterEncoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0);
1469 RegisterEncoding.SGPR0 = TRI->getEncodingValue(AMDGPU::SGPR0);