reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
14418 switch (N->getOpcode()) { 14420 case ISD::ABS: return PerformABSCombine(N, DCI, Subtarget); 14421 case ARMISD::ADDE: return PerformADDECombine(N, DCI, Subtarget); 14422 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); 14423 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 14424 case ISD::SUB: return PerformSUBCombine(N, DCI); 14425 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 14426 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 14427 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); 14428 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); 14430 case ISD::BR_CC: return PerformHWLoopCombine(N, DCI, Subtarget); 14432 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); 14433 case ARMISD::SUBE: return PerformAddeSubeCombine(N, DCI, Subtarget); 14434 case ARMISD::BFI: return PerformBFICombine(N, DCI); 14435 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget); 14436 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 14437 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget); 14438 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget); 14439 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 14440 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 14441 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 14442 case ARMISD::VDUP: return PerformVDUPCombine(N, DCI, Subtarget); 14445 return PerformVCVTCombine(N, DCI.DAG, Subtarget); 14447 return PerformVDIVCombine(N, DCI.DAG, Subtarget); 14448 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 14452 return PerformShiftCombine(N, DCI, Subtarget); 14455 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 14456 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 14457 case ARMISD::BRCOND: return PerformBRCONDCombine(N, DCI.DAG); 14458 case ISD::LOAD: return PerformLOADCombine(N, DCI); 14463 return PerformVLDCombine(N, DCI); 14465 return PerformARMBUILD_VECTORCombine(N, DCI); 14467 return PerformPREDICATE_CASTCombine(N, DCI); 14469 unsigned BitWidth = N->getValueType(0).getSizeInBits(); 14471 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) 14476 unsigned BitWidth = N->getValueType(0).getSizeInBits(); 14478 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) 14485 unsigned BitWidth = N->getValueType(0).getSizeInBits(); 14487 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || 14488 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) 14493 unsigned LowWidth = N->getOperand(0).getValueType().getSizeInBits(); 14495 unsigned HighWidth = N->getOperand(1).getValueType().getSizeInBits(); 14497 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) || 14498 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI))) 14503 unsigned HighWidth = N->getOperand(0).getValueType().getSizeInBits(); 14505 unsigned LowWidth = N->getOperand(1).getValueType().getSizeInBits(); 14507 if ((SimplifyDemandedBits(N->getOperand(0), HighMask, DCI)) || 14508 (SimplifyDemandedBits(N->getOperand(1), LowMask, DCI))) 14513 unsigned BitWidth = N->getValueType(0).getSizeInBits(); 14515 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || 14516 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) 14522 unsigned BitWidth = N->getValueType(0).getSizeInBits(); 14524 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || 14525 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) 14531 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 14555 return PerformVLDCombine(N, DCI);