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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
lib/Target/Hexagon/HexagonBitTracker.cpp 325 return rr0(eIMM(im(1), W0), Outputs);
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
329 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
329 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
347 uint16_t RW = W0;
356 uint16_t RW = W0;
372 assert(W0 == 64 && W1 == 32);
373 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
381 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
383 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
387 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
391 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
395 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
396 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
396 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
401 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
401 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
405 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
406 RegisterCell RC = eADD(rc(1), lo(M, W0));
410 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
411 RegisterCell RC = eADD(rc(1), lo(M, W0));
416 RegisterCell RC = eADD(rc(1), lo(M, W0));
420 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
424 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
440 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
442 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
448 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
450 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
454 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
458 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
467 return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
471 return rr0(hi(M, W0), Outputs);
481 return rr0(lo(M, W0), Outputs);
484 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
485 RegisterCell RC = eADD(rc(1), lo(M, W0));
489 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
490 RegisterCell RC = eSUB(rc(1), lo(M, W0));
495 RegisterCell RC = eADD(rc(1), lo(M, W0));
499 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
503 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
507 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
512 return rr0(hi(M, W0), Outputs);
525 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
533 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
537 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
549 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
557 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
561 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
570 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
574 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
641 assert(W0 == 32);
642 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
642 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
643 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
644 return rr0(eXTR(RC, 0, W0), Outputs);
651 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
651 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
652 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
653 return rr0(eXTR(RC, 0, W0), Outputs);
704 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
705 .fill(W1+(W1-BX), W0, Zero);
715 assert(Wd <= W0);
717 return rr0(eIMM(0, W0), Outputs);
720 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
720 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
723 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
731 assert(Wd < W0 && Of < W0);
731 assert(Wd < W0 && Of < W0);
733 if (Wd+Of > W0)
734 Wd = W0-Of;
748 assert(W0 % 2 == 0);
749 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
749 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
754 assert(W0 == 32);
766 assert(W0 == 64);
791 uint16_t WR = W0;
811 RegisterCell R2 = cop(2, W0);
812 RegisterCell R3 = cop(3, W0);
830 assert(W0 == 64 && W1 == 32);
842 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
844 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
846 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs);
848 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs);
891 RegisterCell RC(W0);
892 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
908 RegisterCell RC(W0);
909 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
955 return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
955 return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);