reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
586 assert(validateBranchCond(Cond) && "Invalid branching condition"); 593 if (!Cond.empty() && Cond[0].isImm()) 593 if (!Cond.empty() && Cond[0].isImm()) 594 BccOpc = Cond[0].getImm(); 597 if (Cond.empty()) { 613 } else if (isEndLoopN(Cond[0].getImm())) { 614 int EndLoopOp = Cond[0].getImm(); 615 assert(Cond[1].isMBB()); 619 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(), 625 } else if (isNewValueJump(Cond[0].getImm())) { 626 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump"); 630 unsigned Flags1 = getUndefRegState(Cond[1].isUndef()); 633 if (Cond[2].isReg()) { 634 unsigned Flags2 = getUndefRegState(Cond[2].isUndef()); 635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). 636 addReg(Cond[2].getReg(), Flags2).addMBB(TBB); 637 } else if(Cond[2].isImm()) { 638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). 639 addImm(Cond[2].getImm()).addMBB(TBB); 643 assert((Cond.size() == 2) && "Malformed cond vector"); 644 const MachineOperand &RO = Cond[1]; 650 assert((!Cond.empty()) && 652 assert((!isNewValueJump(Cond[0].getImm())) && 655 if (isEndLoopN(Cond[0].getImm())) { 656 int EndLoopOp = Cond[0].getImm(); 657 assert(Cond[1].isMBB()); 661 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(), 668 const MachineOperand &RO = Cond[1];