reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); 333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); 370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); 373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); 381 emitInst(Mips::LUi, TmpReg).addImm(Hi); 382 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); 384 emitInst(Mips::LUi, ResultReg).addImm(Hi); 397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); 405 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); 422 emitInst(Mips::LW, DestReg) 428 emitInst(Mips::ADDiu, TempReg) 439 emitInst(Mips::LW, DestReg) 654 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); 655 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); 660 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); 661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); 665 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); 668 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); 672 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); 673 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); 678 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); 679 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); 683 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); 686 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); 690 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); 691 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); 696 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); 697 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); 743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); 744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); 747 emitInst(CondMovOpc, ResultReg) 1013 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); 1067 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); 1068 emitInst(CondMovOpc, ResultReg) 1093 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); 1132 emitInst(Opc, TempReg).addReg(SrcReg); 1133 emitInst(Mips::MFC1, DestReg).addReg(TempReg); 1560 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); 1608 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); 1618 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); 1619 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); 1620 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); 1621 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); 1628 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); 1629 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); 1640 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); 1641 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); 1642 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); 1643 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); 1645 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); 1646 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); 1648 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); 1649 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); 1650 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); 1846 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); 1847 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); 1857 emitInst(Mips::SEB, DestReg).addReg(SrcReg); 1860 emitInst(Mips::SEH, DestReg).addReg(SrcReg); 1893 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); 1956 emitInst(MFOpc, ResultReg); 2009 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); 2032 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); 2119 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());