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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenGlobalISel.inc 642 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
lib/Target/Mips/MipsInstructionSelector.cpp 106 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
136 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
142 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
148 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI);
156 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
158 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
245 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
249 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI))
269 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
273 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI))
276 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
279 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
286 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
294 I.setDesc(TII.get(COPY));
298 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
305 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
318 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
322 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
326 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
330 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
335 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
341 if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
347 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
352 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
357 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
359 if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
366 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
381 I.setDesc(TII.get(TargetOpcode::PHI));
413 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
430 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
434 if (!constrainSelectedInstRegOperands(*PseudoDIV, TII, TRI, RBI))
438 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
441 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
449 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
457 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
490 if (!MTC1.constrainAllUses(TII, TRI, RBI))
505 if (!PairF64.constrainAllUses(TII, TRI, RBI))
517 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
536 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
539 if (!constrainSelectedInstRegOperands(*Trunc, TII, TRI, RBI))
542 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
545 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
554 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
570 if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI))
578 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
583 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
589 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
593 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
597 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
602 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI))
610 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
620 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
699 if (!MIB.constrainAllUses(TII, TRI, RBI))
757 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
766 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode))
770 if (!constrainSelectedInstRegOperands(*FCMP, TII, TRI, RBI))
773 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
778 if (!constrainSelectedInstRegOperands(*Move, TII, TRI, RBI))
785 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
794 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
798 if (!constrainSelectedInstRegOperands(*LEA_ADDiu, TII, TRI, RBI))
801 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))
805 if (!constrainSelectedInstRegOperands(*Store, TII, TRI, RBI))
816 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);