reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
307 if (MI.isDebugInstr()) 311 switch (MI.getOpcode()) { 324 if (TII->isTOCSaveMI(MI)) 325 UpdateTOCSaves(TOCSaves, &MI); 332 int Immed = MI.getOperand(3).getImm(); 343 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 345 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); 371 LLVM_DEBUG(MI.dump()); 372 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 372 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 373 MI.getOperand(0).getReg()) 374 .add(MI.getOperand(1)); 375 ToErase = &MI; 392 LLVM_DEBUG(MI.dump()); 393 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 393 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 394 MI.getOperand(0).getReg()) 395 .add(MI.getOperand(1)); 396 ToErase = &MI; 406 LLVM_DEBUG(MI.dump()); 407 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg()); 408 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg()); 409 MI.getOperand(3).setImm(3 - Immed); 417 LLVM_DEBUG(MI.dump()); 418 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 418 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 419 MI.getOperand(0).getReg()) 421 ToErase = &MI; 429 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 430 ToErase = &MI; 433 LLVM_DEBUG(MI.dump()); 442 unsigned MyOpcode = MI.getOpcode(); 445 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI); 473 LLVM_DEBUG(MI.dump()); 474 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 474 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 475 MI.getOperand(0).getReg()) 476 .add(MI.getOperand(OpNo)); 477 ToErase = &MI; 487 unsigned SplatImm = MI.getOperand(2).getImm(); 498 LLVM_DEBUG(MI.dump()); 499 MI.getOperand(1).setReg(ShiftOp1); 500 MI.getOperand(2).setImm(NewElem); 508 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); 545 LLVM_DEBUG(MI.dump()); 568 Register NarrowReg = MI.getOperand(1).getReg(); 593 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 598 LLVM_DEBUG(MI.dump()); 601 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 602 ToErase = &MI; 612 Register NarrowReg = MI.getOperand(1).getReg(); 637 unsigned Opc = getSextLoadOp(is64Bit(MI.getOpcode()), 642 LLVM_DEBUG(MI.dump()); 645 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); 646 ToErase = &MI; 649 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && 656 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 656 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), 658 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 658 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), 659 MI.getOperand(0).getReg()) 663 ToErase = &MI; 678 if (MI.getOperand(2).getImm() != 0) 681 Register SrcReg = MI.getOperand(1).getReg(); 703 if (MI.getOperand(3).getImm() <= KnownZeroCount) { 705 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 705 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 706 MI.getOperand(0).getReg()) 708 ToErase = &MI; 751 MachineOperand Op1 = MI.getOperand(1); 752 MachineOperand Op2 = MI.getOperand(2); 761 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 794 LLVM_DEBUG(MI.dump()); 795 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 795 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), 796 MI.getOperand(0).getReg()) 798 ToErase = &MI; 804 Simplified |= emitRLDICWhenLoweringJumpTables(MI) || 805 combineSEXTAndSHL(MI, ToErase);