reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp

  387   const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg);
  408       printOperand(MI, Op + X86::AddrBaseReg, O);

lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp

  346   const MCOperand &BaseReg  = MI->getOperand(Op+X86::AddrBaseReg);
  358     printOperand(MI, Op+X86::AddrBaseReg, O);

lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp

   67     const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
  209   const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
  230   const MCOperand &BaseReg  = MI.getOperand(Op+X86::AddrBaseReg);
  383   const MCOperand &Base     = MI.getOperand(Op+X86::AddrBaseReg);
  763     unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
  808     unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
  823     unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
  839     unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
  861     unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg);
 1088     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
 1097     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B
 1107     REX |= isREXExtendedReg(MI, MemOperand+X86::AddrBaseReg) << 0; // REX.B

lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

  534   const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg);

lib/Target/X86/X86AsmPrinter.cpp

  278   const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
  315       PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier);
  341   const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
  357     PrintOperand(MI, OpNo + X86::AddrBaseReg, O);

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  299   return MI->getOperand(AddrOffset + X86::AddrBaseReg);

lib/Target/X86/X86CallFrameOptimization.cpp

  427     if (!I->getOperand(X86::AddrBaseReg).isReg() ||
  428         (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||

lib/Target/X86/X86FixupLEAs.cpp

  357   const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);
  450     MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
  486   const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);
  536   const MachineOperand &Base =    MI.getOperand(1 + X86::AddrBaseReg);

lib/Target/X86/X86InsertPrefetch.cpp

   82   Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
  217         assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
  225         MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg())

lib/Target/X86/X86InstrInfo.cpp

  195   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
  202     FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
  600     if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
  605       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
  625       if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
  627       Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
 3205   BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
 5925   if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) ||

lib/Target/X86/X86InstrInfo.h

  116          MI.getOperand(Op + X86::AddrBaseReg).isReg() &&

lib/Target/X86/X86MCInstLower.cpp

  355       Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
  379       (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||

lib/Target/X86/X86OptimizeLEAs.cpp

  191   return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg),
  356     if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
  451     if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO))
  457       if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) &&
  552     MI.getOperand(MemOpNo + X86::AddrBaseReg)

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1713             MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);
 1786               MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);
 2184             UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);