reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
897 if (hasLiveCondCodeDef(MI)) 900 MachineFunction &MF = *MI.getParent()->getParent(); 902 const MachineOperand &Dest = MI.getOperand(0); 903 const MachineOperand &Src = MI.getOperand(1); 911 if (MI.getNumOperands() > 2) 912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef()) 912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef()) 919 unsigned MIOpc = MI.getOpcode(); 923 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); 924 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 933 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)) 943 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); 944 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 953 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, 958 BuildMI(MF, MI.getDebugLoc(), get(Opc)) 975 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!"); 976 unsigned ShAmt = getTruncatedShiftCount(MI, 2); 979 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp); 983 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!"); 989 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill, 994 BuildMI(MF, MI.getDebugLoc(), get(Opc)) 1005 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!"); 1012 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, SrcReg, isKill, 1016 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 1032 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp); 1037 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 1047 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 1051 const MachineOperand &Src2 = MI.getOperand(2); 1055 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 1059 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest); 1067 LV->replaceKillInstruction(SrcReg2, MI, *NewMI); 1076 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp); 1081 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 1083 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src), 1084 MI.getOperand(2)); 1090 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 1096 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 1100 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 1106 NewMI = addOffset(MIB, MI.getOperand(2)); 1117 return convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV, Is8BitOp); 1125 if (!MI.getOperand(2).isImm()) 1127 int64_t Imm = MI.getOperand(2).getImm(); 1131 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!"); 1137 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, 1141 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 1153 if (!MI.getOperand(2).isImm()) 1155 int64_t Imm = MI.getOperand(2).getImm(); 1159 assert(MI.getNumOperands() >= 3 && "Unknown sub instruction!"); 1161 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), 1242 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 1244 .add(MI.getOperand(2)) 1246 .add(MI.getOperand(3)) 1247 .add(MI.getOperand(4)) 1248 .add(MI.getOperand(5)) 1249 .add(MI.getOperand(6)) 1250 .add(MI.getOperand(7)); 1307 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc)) 1309 .add(MI.getOperand(2)) 1311 .add(MI.getOperand(3)); 1320 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI); 1322 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI); 1325 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst