reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
4082 return Expand2AddrUndef(MIB, get(X86::XOR32rr)); 4084 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false); 4086 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true); 4089 return ExpandMOVImmSExti8(MIB, *this, Subtarget); 4091 return Expand2AddrUndef(MIB, get(X86::SBB8rr)); 4093 return Expand2AddrUndef(MIB, get(X86::SBB16rr)); 4095 return Expand2AddrUndef(MIB, get(X86::SBB32rr)); 4097 return Expand2AddrUndef(MIB, get(X86::SBB64rr)); 4099 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr)); 4104 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr)); 4108 Register SrcReg = MIB->getOperand(0).getReg(); 4110 MIB->getOperand(0).setReg(XReg); 4111 Expand2AddrUndef(MIB, get(X86::VXORPSrr)); 4112 MIB.addReg(SrcReg, RegState::ImplicitDefine); 4120 Register SrcReg = MIB->getOperand(0).getReg(); 4123 return Expand2AddrUndef(MIB, 4128 MIB->getOperand(0).setReg(SrcReg); 4129 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 4134 Register SrcReg = MIB->getOperand(0).getReg(); 4138 MIB->getOperand(0).setReg(XReg); 4139 Expand2AddrUndef(MIB, 4141 MIB.addReg(SrcReg, RegState::ImplicitDefine); 4148 MIB->getOperand(0).setReg(ZReg); 4150 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr)); 4153 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr)); 4155 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr)); 4157 Register Reg = MIB->getOperand(0).getReg(); 4159 MIB->setDesc(get(X86::VCMPPSYrri)); 4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf); 4164 Register Reg = MIB->getOperand(0).getReg(); 4165 MIB->setDesc(get(X86::VPTERNLOGDZrri)); 4168 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef) 4174 Register Reg = MIB->getOperand(0).getReg(); 4175 Register MaskReg = MIB->getOperand(1).getReg(); 4176 unsigned MaskState = getRegState(MIB->getOperand(1)); 4180 MIB->setDesc(get(Opc)); 4183 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) 4188 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm), 4191 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm), 4194 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm), 4197 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm), 4200 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr), 4203 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr), 4206 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr), 4209 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr), 4212 Register Reg = MIB->getOperand(0).getReg(); 4215 MIB->getOperand(0).setReg(Reg32); 4216 MIB.addReg(Reg, RegState::ImplicitDefine); 4227 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0); 4228 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0); 4229 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0); 4230 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0); 4231 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0); 4232 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0); 4234 expandLoadStackGuard(MIB, *this); 4238 return expandXorFP(MIB, *this); 4239 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8)); 4240 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8)); 4241 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8)); 4242 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8)); 4243 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break; 4244 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break; 4245 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break; 4246 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break; 4247 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break; 4248 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break; 4249 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break; 4250 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break; 4251 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break; 4252 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break; 4253 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;