1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
define void @test_extload() {
entry:
ret void
}
define i64 @sext_i32_i64(i32* %ptr) {
%ld = load i32, i32* %ptr, align 4
%v = sext i32 %ld to i64
ret i64 %v
}
define i64 @sext_i16_i64(i16* %ptr) {
%ld = load i16, i16* %ptr, align 2
%v = sext i16 %ld to i64
ret i64 %v
}
define i64 @sext_i8_i64(i8* %ptr) {
%ld = load i8, i8* %ptr, align 1
%v = sext i8 %ld to i64
ret i64 %v
}
define i64 @zext_i32_i64(i32* %ptr) {
%ld = load i32, i32* %ptr, align 4
%v = zext i32 %ld to i64
ret i64 %v
}
define i64 @zext_i16_i64(i16* %ptr) {
%ld = load i16, i16* %ptr, align 2
%v = zext i16 %ld to i64
ret i64 %v
}
define i64 @zext_i8_i64(i8* %ptr) {
%ld = load i8, i8* %ptr, align 1
%v = zext i8 %ld to i64
ret i64 %v
}
...
---
name: test_extload
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_extload
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_LOAD %0 :: (load 1)
$w0 = COPY %1
...
---
name: sext_i32_i64
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: sext_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 4 from %ir.ptr)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
---
name: sext_i16_i64
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: sext_i16_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr)
; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.ptr)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
---
name: sext_i8_i64
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: sext_i8_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s64) = G_SEXTLOAD [[COPY]](p0) :: (load 1 from %ir.ptr)
; CHECK: $x0 = COPY [[SEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%2:_(s64) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.ptr)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
---
name: zext_i32_i64
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: zext_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 4 from %ir.ptr)
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 4 from %ir.ptr)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
---
name: zext_i16_i64
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: zext_i16_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr)
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.ptr)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
---
name: zext_i8_i64
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: zext_i8_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load 1 from %ir.ptr)
; CHECK: $x0 = COPY [[ZEXTLOAD]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(p0) = COPY $x0
%2:_(s64) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.ptr)
$x0 = COPY %2(s64)
RET_ReallyLR implicit $x0
...
|