1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @fld(double *%a) nounwind {
; RV32IFD-LABEL: fld:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: fld ft1, 24(a0)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fld:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fld ft0, 0(a0)
; RV64IFD-NEXT: fld ft1, 24(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = load double, double* %a
%2 = getelementptr double, double* %a, i32 3
%3 = load double, double* %2
; Use both loaded values in an FP op to ensure an fld is used, even for the
; soft float ABI
%4 = fadd double %1, %3
ret double %4
}
define void @fsd(double *%a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fsd:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a3, 8(sp)
; RV32IFD-NEXT: sw a4, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a1, 8(sp)
; RV32IFD-NEXT: sw a2, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 0(a0)
; RV32IFD-NEXT: fsd ft0, 64(a0)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsd:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, 0(a0)
; RV64IFD-NEXT: fsd ft0, 64(a0)
; RV64IFD-NEXT: ret
; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI
%1 = fadd double %b, %c
store double %1, double* %a
%2 = getelementptr double, double* %a, i32 8
store double %1, double* %2
ret void
}
; Check load and store to a global
@G = global double 0.0
define double @fld_fsd_global(double %a, double %b) nounwind {
; RV32IFD-LABEL: fld_fsd_global:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: lui a0, %hi(G)
; RV32IFD-NEXT: fld ft1, %lo(G)(a0)
; RV32IFD-NEXT: fsd ft0, %lo(G)(a0)
; RV32IFD-NEXT: addi a0, a0, %lo(G)
; RV32IFD-NEXT: fld ft1, 72(a0)
; RV32IFD-NEXT: fsd ft0, 72(a0)
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fld_fsd_global:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: lui a0, %hi(G)
; RV64IFD-NEXT: fld ft1, %lo(G)(a0)
; RV64IFD-NEXT: fsd ft0, %lo(G)(a0)
; RV64IFD-NEXT: addi a1, a0, %lo(G)
; RV64IFD-NEXT: fld ft1, 72(a1)
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 72(a1)
; RV64IFD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI
%1 = fadd double %a, %b
%2 = load volatile double, double* @G
store double %1, double* @G
%3 = getelementptr double, double* @G, i32 9
%4 = load volatile double, double* %3
store double %1, double* %3
ret double %1
}
; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
define double @fld_fsd_constant(double %a) nounwind {
; RV32IFD-LABEL: fld_fsd_constant:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: lui a0, 912092
; RV32IFD-NEXT: fld ft1, -273(a0)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, -273(a0)
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fld_fsd_constant:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: lui a1, 56
; RV64IFD-NEXT: addiw a1, a1, -1353
; RV64IFD-NEXT: slli a1, a1, 14
; RV64IFD-NEXT: fld ft0, -273(a1)
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, -273(a1)
; RV64IFD-NEXT: ret
%1 = inttoptr i32 3735928559 to double*
%2 = load volatile double, double* %1
%3 = fadd double %a, %2
store double %3, double* %1
ret double %3
}
declare void @notdead(i8*)
define double @fld_stack(double %a) nounwind {
; RV32IFD-LABEL: fld_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fld_stack:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp)
; RV64IFD-NEXT: addi a0, sp, 16
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: fld ft0, 16(sp)
; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret
%1 = alloca double, align 8
%2 = bitcast double* %1 to i8*
call void @notdead(i8* %2)
%3 = load double, double* %1
%4 = fadd double %3, %a ; force load in to FPR64
ret double %4
}
define void @fsd_stack(double %a, double %b) nounwind {
; RV32IFD-LABEL: fsd_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsd_stack:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp)
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
%1 = fadd double %a, %b ; force store from FPR64
%2 = alloca double, align 8
store double %1, double* %2
%3 = bitcast double* %2 to i8*
call void @notdead(i8* %3)
ret void
}
; Test selection of store<ST4[%a], trunc to f32>, ..
define void @fsd_trunc(float* %a, double %b) nounwind noinline optnone {
; RV32IFD-LABEL: fsd_trunc:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a1, 8(sp)
; RV32IFD-NEXT: sw a2, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fcvt.s.d ft0, ft0
; RV32IFD-NEXT: fsw ft0, 0(a0)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsd_trunc:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fcvt.s.d ft0, ft0
; RV64IFD-NEXT: fsw ft0, 0(a0)
; RV64IFD-NEXT: ret
%1 = fptrunc double %b to float
store float %1, float* %a, align 4
ret void
}
|