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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
utils/TableGen/AsmMatcherEmitter.cpp 543 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
1507 if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1511 if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1515 StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");
1542 if (!StringRef(Alias->ResultInst->TheDef->getName())
2041 II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
3444 << MI->getResultInst()->TheDef->getName() << ", "
utils/TableGen/AsmWriterEmitter.cpp 125 << FirstInst.CGI->TheDef->getName() << ":\n";
128 << AWI.CGI->TheDef->getName() << ":\n";
140 FirstInst.CGI->TheDef->getName().str(),
145 AWI.CGI->TheDef->getName().str(),
183 InstrsForCase[idx] += Inst.CGI->TheDef->getName();
187 InstrsForCase.push_back(Inst.CGI->TheDef->getName());
403 << NumberedInstructions[i]->TheDef->getName() << "\n";
1144 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
utils/TableGen/AsmWriterInst.cpp 97 CGI.TheDef->getLoc(),
99 CGI.TheDef->getName() + "'!");
137 CGI.TheDef->getLoc(),
139 CGI.TheDef->getName() + "'");
146 CGI.TheDef->getLoc(),
148 CGI.TheDef->getName() + "'");
156 PrintFatalError(CGI.TheDef->getLoc(),
158 CGI.TheDef->getName() + "'");
163 CGI.TheDef->getLoc(),
165 CGI.TheDef->getName() + "'");
169 PrintFatalError(CGI.TheDef->getLoc(),
170 "Stray '$' in '" + CGI.TheDef->getName() +
utils/TableGen/CodeEmitterGen.cpp 358 Record *R = CGI->TheDef;
404 Record *R = CGI->TheDef;
553 for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
615 for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
624 o << ", // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
utils/TableGen/CodeGenDAGPatterns.cpp 3604 assert(!DAGInsts.count(CGI.TheDef) && "Instruction already parsed!");
3607 TreePattern I(CGI.TheDef, Pat, true, *this);
3971 PrintError(InstInfo->TheDef->getLoc(),
3974 PrintError(InstInfo->TheDef->getLoc(),
3977 PrintError(InstInfo->TheDef->getLoc(),
4040 InstInfo.InferredFrom != InstInfo.TheDef &&
utils/TableGen/CodeGenInstruction.cpp 508 if (DagInit *ConstraintList = TheDef->getValueAsDag("InOperandList")) {
utils/TableGen/CodeGenMapTable.cpp 385 Record *CurInstr = NumberedInstructions[i]->TheDef;
utils/TableGen/CodeGenSchedule.cpp 121 StringRef InstName = Inst->TheDef->getName();
124 Elts.insert(Inst->TheDef);
134 return LHS->TheDef->getName() < RHS;
137 return LHS < RHS->TheDef->getName() &&
138 !RHS->TheDef->getName().startswith(LHS);
149 StringRef InstName = Inst->TheDef->getName();
151 Elts.insert(Inst->TheDef);
600 Record *SchedDef = Inst->TheDef;
876 Record *ItinDef = Inst->TheDef->getValueAsDef("Itinerary");
878 if (!Inst->TheDef->isValueUnset("SchedRW"))
879 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
883 InstrClassMap[Inst->TheDef] = SCIdx;
903 StringRef InstName = Inst->TheDef->getName();
908 dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
914 PrintFatalError(Inst->TheDef->getLoc(), "Instruction's sched class "
959 dbgs() << "No machine model for " << Inst->TheDef->getName()
970 return InstrClassMap.lookup(Inst.TheDef);
1943 if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
1944 PrintError(Inst->TheDef->getLoc(),
1946 Inst->TheDef->getName() + "' in SchedMachineModel '" +
1965 PrintError(Inst->TheDef->getLoc(), "'" + ProcModel.ModelName +
1967 Inst->TheDef->getName() + "'");
2154 for (const Record *PredDef : Inst.TheDef->getValueAsListOfDefs("Predicates")) {
utils/TableGen/CodeGenTarget.cpp 449 if (CGI->TheDef->getValueAsBit("isPseudo"))
460 const auto &D1 = *Rec1->TheDef;
461 const auto &D2 = *Rec2->TheDef;
utils/TableGen/DAGISelMatcherGen.cpp 959 AddMatcher(new EmitNodeMatcher(II.Namespace.str()+"::"+II.TheDef->getName().str(),
utils/TableGen/FixedLenDecoderEmitter.cpp 118 if (Value.EncodingDef != Value.Inst->TheDef)
120 OS << Value.Inst->TheDef->getName();
442 const Record *InstDef = AllInstructions[Opcode].Inst->TheDef;
1798 const Record &Def = *CGI.TheDef;
2394 IndexOfInstruction[NumberedInstruction->TheDef] = NumberedEncodings.size();
2397 NumberedInstruction->TheDef->getValue("EncodingInfos")) {
2412 IndexOfInstruction[NumberedInstruction->TheDef] = NumberedEncodings.size();
2415 NumberedInstruction->TheDef->getValue("EncodingInfos")) {
2430 NumberedEncodings.emplace_back(NumberedInstruction->TheDef,
2445 const Record *Def = Inst->TheDef;
utils/TableGen/GlobalISelEmitter.cpp 1672 return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(),
1674 return MatchTable::NamedValue(I->Namespace, I->TheDef->getName());
1700 return I->TheDef->getName() < BO->I->TheDef->getName();
1700 return I->TheDef->getName() < BO->I->TheDef->getName();
1706 return I->TheDef->getName() == "G_CONSTANT";
1709 StringRef getOpcode() const { return I->TheDef->getName(); }
2822 << MatchTable::NamedValue(I->Namespace, I->TheDef->getName())
2853 << MatchTable::NamedValue(I->Namespace, I->TheDef->getName())
3677 if (SrcGIOrNull->TheDef->getName() == "G_CONSTANT" ||
3678 SrcGIOrNull->TheDef->getName() == "G_FCONSTANT") {
3691 bool IsFCmp = SrcGIOrNull->TheDef->getName() == "G_FCMP";
3693 if (IsFCmp || SrcGIOrNull->TheDef->getName() == "G_ICMP") {
3716 SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" ||
3717 SrcGIOrNull->TheDef->getName() == "G_INTRINSIC_W_SIDE_EFFECTS";
4129 auto OpName = Target.getInstruction(Dst->getOperator()).TheDef->getName();
4216 StringRef Name = DstI->TheDef->getName();
4239 StringRef Name = OrigDstI->TheDef->getName();
4447 StringRef InstName = Inst.TheDef->getName();
4616 StringRef DstIName = DstI.TheDef->getName();
utils/TableGen/InstrDocsEmitter.cpp 70 Record *Inst = II->TheDef;
219 II->TheDef->getValueAsListOfDefs("Predicates");
utils/TableGen/InstrInfoEmitter.cpp 229 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
242 Inst->TheDef->getName().str());
531 Record *Inst = II->TheDef;
559 InstrNames.add(Inst->TheDef->getName());
577 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
659 << Inst.TheDef->getValueAsInt("Size") << ",\t"
708 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
710 PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
716 PrintFatalError(Inst.TheDef->getLoc(),
717 "Invalid TSFlags bit in " + Inst.TheDef->getName());
724 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
730 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
755 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
777 OS << " " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
utils/TableGen/PseudoLoweringEmitter.cpp 212 << Source.TheDef->getName() << ": {\n"
216 << Dest.TheDef->getName() << ");\n";
utils/TableGen/RISCVCompressInstEmitter.cpp 256 PrintFatalError(Inst.TheDef->getLoc(),
257 "Input operands for Inst '" + Inst.TheDef->getName() +
261 PrintFatalError(Inst.TheDef->getLoc(),
262 "Inst '" + Inst.TheDef->getName() +
273 PrintFatalError(Inst.TheDef->getLoc(),
274 "Inst '" + Inst.TheDef->getName() +
539 return (LHS.Source.TheDef->getName().str() <
540 RHS.Source.TheDef->getName().str());
542 return (LHS.Dest.TheDef->getName().str() <
543 RHS.Dest.TheDef->getName().str());
605 CurOp = Source.TheDef->getName().str();
619 std::vector<Record *> RF = Dest.TheDef->getValueAsListOfDefs("Predicates");
674 "::" + Dest.TheDef->getName().str() + ");\n";
utils/TableGen/WebAssemblyDisassemblerEmitter.cpp 33 auto &Def = *CGI.TheDef;
60 auto IsCanonicalExisting = CGIP.second->TheDef->getValue("IsCanonical")
utils/TableGen/X86EVEX2VEXTablesEmitter.cpp 63 OS << " { X86::" << Pair.first->TheDef->getName()
64 << ", X86::" << Pair.second->TheDef->getName() << " },\n";
92 Record *RecE = EVEXInst->TheDef;
93 Record *RecV = VEXInst->TheDef;
179 if (!Inst->TheDef->isSubClassOf("X86Inst"))
184 if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncVEX") {
185 uint64_t Opcode = getValueFromBitsInit(Inst->TheDef->
190 else if (Inst->TheDef->getValueAsDef("OpEnc")->getName() == "EncEVEX" &&
191 !Inst->TheDef->getValueAsBit("hasEVEX_K") &&
192 !Inst->TheDef->getValueAsBit("hasEVEX_B") &&
193 !Inst->TheDef->getValueAsBit("hasEVEX_L2") &&
194 !Inst->TheDef->getValueAsBit("notEVEX2VEXConvertible"))
199 uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
205 if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
207 EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
221 if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
utils/TableGen/X86FoldTablesEmitter.cpp 82 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
88 return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
114 OS << "{ X86::" << RegInst->TheDef->getName() << ",";
116 OS << "X86::" << MemInst->TheDef->getName() << ",";
302 StringRef AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm");
320 Record *MemRec = MemInst->TheDef;
321 Record *RegRec = RegInst->TheDef;
461 Record *RegRec = RegInstr->TheDef;
462 Record *MemRec = MemInstr->TheDef;
517 Record *RegRec = RegInstr->TheDef;
518 Record *MemRec = MemInstr->TheDef;
587 if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst"))
587 if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst"))
590 const Record *Rec = Inst->TheDef;
619 getValueFromBitsInit(MemInst->TheDef->getValueAsBitsInit("Opcode"));
636 if (RegInst->TheDef->isValueUnset("FoldGenRegForm")) {
utils/TableGen/X86RecognizableInstr.cpp 67 Rec = insn.TheDef;
142 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))