reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1216 for (Record *Pred : ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")) { 1934 if (!ProcModel.ModelDef->getValueAsBit("CompleteModel")) 1947 ProcModel.ModelDef->getName() + "'"); 1962 return R->getValueAsDef("SchedModel") == ProcModel.ModelDef; 2067 && ProcResDef->getValueAsDef("SchedModel") == PM.ModelDef) { 2078 && ProcResGroup->getValueAsDef("SchedModel") == PM.ModelDef) { 2165 << (ModelDef ? ModelDef->getName() : "inferred") << " " 2165 << (ModelDef ? ModelDef->getName() : "inferred") << " "utils/TableGen/SubtargetEmitter.cpp
874 PrintFatalError(ProcModel.ModelDef->getLoc(), 926 PrintFatalError(ProcModel.ModelDef->getLoc(), 1348 PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " 1354 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); 1355 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); 1356 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); 1357 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); 1358 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); 1359 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); 1362 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); 1362 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); 1368 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false); 1368 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false);