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| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Global Combiner *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
#include "llvm/ADT/SparseBitVector.h"
namespace llvm {
extern cl::OptionCategory GICombinerOptionCategory;
} // end namespace llvm
#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
class AArch64GenPreLegalizerCombinerHelper {
SparseBitVector<> DisabledRules;
public:
bool parseCommandLineOption();
bool isRuleDisabled(unsigned ID) const;
bool setRuleDisabled(StringRef RuleIdentifier);
bool tryCombineAll(
GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const;
};
static Optional<uint64_t> getRuleIdxForIdentifier(StringRef RuleIdentifier) {
uint64_t I;
// getAtInteger(...) returns false on success
bool Parsed = !RuleIdentifier.getAsInteger(0, I);
if (Parsed)
return I;
#ifndef NDEBUG
switch (RuleIdentifier.size()) {
default: break;
case 9: // 1 string to match.
if (memcmp(RuleIdentifier.data()+0, "copy_prop", 9) != 0)
break;
return 0; // "copy_prop"
case 26: // 1 string to match.
if (memcmp(RuleIdentifier.data()+0, "elide_br_by_inverting_cond", 26) != 0)
break;
return 1; // "elide_br_by_inverting_cond"
}
#endif // ifndef NDEBUG
return None;
}
bool AArch64GenPreLegalizerCombinerHelper::setRuleDisabled(StringRef RuleIdentifier) {
std::pair<StringRef, StringRef> RangePair = RuleIdentifier.split('-');
if (!RangePair.second.empty()) {
const auto First = getRuleIdxForIdentifier(RangePair.first);
const auto Last = getRuleIdxForIdentifier(RangePair.second);
if (!First.hasValue() || !Last.hasValue())
return false;
if (First >= Last)
report_fatal_error("Beginning of range should be before end of range");
for (auto I = First.getValue(); I < Last.getValue(); ++I)
DisabledRules.set(I);
return true;
} else {
const auto I = getRuleIdxForIdentifier(RangePair.first);
if (!I.hasValue())
return false;
DisabledRules.set(I.getValue());
return true;
}
return false;
}
bool AArch64GenPreLegalizerCombinerHelper::isRuleDisabled(unsigned RuleID) const {
return DisabledRules.test(RuleID);
}
#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
#ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
cl::list<std::string> AArch64PreLegalizerCombinerHelperOption(
"aarch64prelegalizercombinerhelper-disable-rule",
cl::desc("Disable one or more combiner rules temporarily in the AArch64PreLegalizerCombinerHelper pass"),
cl::CommaSeparated,
cl::Hidden,
cl::cat(GICombinerOptionCategory));
bool AArch64GenPreLegalizerCombinerHelper::parseCommandLineOption() {
for (const auto &Identifier : AArch64PreLegalizerCombinerHelperOption)
if (!setRuleDisabled(Identifier))
return false;
return true;
}
bool AArch64GenPreLegalizerCombinerHelper::tryCombineAll(
GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
CombinerHelper Helper(Observer, B);
MachineBasicBlock *MBB = MI.getParent();
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
(void)MBB; (void)MF; (void)MRI;
// Rule: copy_prop
if (!isRuleDisabled(0)) {
if (1
&& [&]() {
return Helper.matchCombineCopy(MI);
return true;
}()) {
Helper.applyCombineCopy(MI);
return true;
}
}
// Rule: elide_br_by_inverting_cond
if (!isRuleDisabled(1)) {
if (1
&& [&]() {
return Helper.matchElideBrByInvertingCond(MI);
return true;
}()) {
Helper.applyElideBrByInvertingCond(MI);
return true;
}
}
return false;
}
#endif // ifdef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
|