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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 8928 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 16>());
8937 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 32>());
8946 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 64>());
8955 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 8>());
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 6657 static const MCOperandInfo OperandInfo256[] = { { AArch64::ZPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6677 static const MCOperandInfo OperandInfo276[] = { { AArch64::ZPR2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6681 static const MCOperandInfo OperandInfo280[] = { { AArch64::ZPR3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6685 static const MCOperandInfo OperandInfo284[] = { { AArch64::ZPR4RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6754 static const MCOperandInfo OperandInfo353[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
6811 static const MCOperandInfo OperandInfo410[] = { { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
6811 static const MCOperandInfo OperandInfo410[] = { { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
gen/lib/Target/AArch64/AArch64GenRegisterBank.inc 95 (1u << (AArch64::GPR64commonRegClassID - 0)) |
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 3456 { GPR64common, GPR64commonBits, 1698, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true },
6882 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID];
7122 &AArch64MCRegisterClasses[GPR64commonRegClassID],
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 247 case AArch64::GPR64commonRegClassID:
lib/Target/AArch64/AArch64RegisterInfo.cpp 552 case AArch64::GPR64commonRegClassID: