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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 4593 Inst.addOperand(MCOperand::createReg(ARM::R0));
9078 case ARM::R0: OpKind = MCK_Reg11; break;
gen/lib/Target/ARM/ARMGenCallingConv.inc 140 ARM::R0, ARM::R2
143 ARM::R0, ARM::R1
155 ARM::R0, ARM::R1, ARM::R2, ARM::R3
167 ARM::R0, ARM::R1, ARM::R2, ARM::R3
177 ARM::R0, ARM::R1, ARM::R2, ARM::R3
389 ARM::R0, ARM::R1, ARM::R2, ARM::R3
503 if (unsigned Reg = State.AllocateReg(ARM::R0)) {
681 ARM::R0, ARM::R1, ARM::R2, ARM::R3
691 ARM::R0, ARM::R2
854 ARM::R0, ARM::R1, ARM::R2, ARM::R3
864 ARM::R0, ARM::R2
gen/lib/Target/ARM/ARMGenInstrInfo.inc 5300 static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5301 static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5302 static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 };
5310 static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 };
5312 static const MCPhysReg ImplicitList17[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 };
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 1549 { ARM::R0 },
1607 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::PC,
1617 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::APSR_NZCV,
1627 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR, ARM::ZR,
1647 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::LR,
1657 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::APSR,
1667 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::ZR,
1677 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR,
1687 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::PC,
1717 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1727 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R12, ARM::LR,
1767 ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,
1787 ARM::R0, ARM::R2, ARM::R4, ARM::R6,
1807 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1817 ARM::R0, ARM::R2, ARM::R12,
1837 ARM::R0, ARM::R2,
3017 { 0U, ARM::R0 },
3069 { 0U, ARM::R0 },
3157 { ARM::R0, 0U },
3210 { ARM::R0, 0U },
5939 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::PC };
5940 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5941 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP, ARM::PC };
5959 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5960 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5977 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP, ARM::ZR };
5978 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5995 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::SP };
5996 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
5997 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::SP };
6015 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::ZR };
6016 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6033 static const MCPhysReg AltOrder1[] = { ARM::LR, ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12 };
6034 static const MCPhysReg AltOrder2[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
6035 static const MCPhysReg AltOrder3[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::LR, ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
6053 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 };
6085 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
6101 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6 };
6133 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
6149 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 };
6180 static const MCPhysReg AltOrder1[] = { ARM::R0, ARM::R2 };
16011 static const MCPhysReg CSR_AAPCS_ThisReturn_SaveList[] = { ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
16013 static const MCPhysReg CSR_FIQ_SaveList[] = { ARM::LR, ARM::R11, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16017 static const MCPhysReg CSR_GenericInt_SaveList[] = { ARM::LR, ARM::R12, ARM::R11, ARM::R10, ARM::R9, ARM::R8, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R3, ARM::R2, ARM::R1, ARM::R0, 0 };
16035 static const MCPhysReg CSR_iOS_ThisReturn_SaveList[] = { ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, ARM::R0, 0 };
lib/Target/ARM/ARMAsmPrinter.cpp 1879 .addReg(ARM::R0)
1894 .addReg(ARM::R0)
1936 .addReg(ARM::R0)
1956 .addReg(ARM::R0)
lib/Target/ARM/ARMBaseInstrInfo.cpp 4753 if (Reg < ARM::R0 || Reg > ARM::R7) {
lib/Target/ARM/ARMBaseRegisterInfo.h 47 case R0: case R1: case R2: case R3:
lib/Target/ARM/ARMCallingConv.cpp 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
67 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
69 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
70 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
119 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
156 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
lib/Target/ARM/ARMFastISel.cpp 3052 ARM::R0, ARM::R1, ARM::R2, ARM::R3
lib/Target/ARM/ARMFrameLowering.cpp 429 case ARM::R0:
636 case ARM::R0:
1740 case ARM::R0: case ARM::R1:
1756 case ARM::R0: case ARM::R1:
1924 for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
2142 SavedRegs.set(ARM::R0);
lib/Target/ARM/ARMISelLowering.cpp 147 ARM::R0, ARM::R1, ARM::R2, ARM::R3
3112 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3115 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3117 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
4074 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
17079 return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R0;
lib/Target/ARM/ARMInstrInfo.cpp 43 NopInst.addOperand(MCOperand::createReg(ARM::R0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 3905 .Case("a1", ARM::R0)
4251 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
4258 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 1114 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1121 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1239 Register = ARM::R0;
lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h 163 case R0: case R1: case R2: case R3:
lib/Target/ARM/Thumb1FrameLowering.cpp 280 case ARM::R0:
844 for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
876 ARM::R2, ARM::R1, ARM::R0};
974 CopyRegs[ARM::R0] = true;
984 static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
unittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp 35 Check({{ARM::R0, APInt()}},
37 .addReg(ARM::R0)
38 .addReg(ARM::R0)
39 .addReg(ARM::R0)