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| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Calling Convention Implementation Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
static bool CC_BPF32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_BPF64(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool RetCC_BPF32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool RetCC_BPF64(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_BPF32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (LocVT == MVT::i32) {
static const MCPhysReg RegList1[] = {
BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5
};
static const MCPhysReg RegList2[] = {
BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5
};
if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
if (LocVT == MVT::i64) {
static const MCPhysReg RegList3[] = {
BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5
};
static const MCPhysReg RegList4[] = {
BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5
};
if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
unsigned Offset5 = State.AllocateStack(8, 8);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
return false;
return true; // CC didn't match.
}
static bool CC_BPF64(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (LocVT == MVT::i8 ||
LocVT == MVT::i16 ||
LocVT == MVT::i32) {
LocVT = MVT::i64;
if (ArgFlags.isSExt())
LocInfo = CCValAssign::SExt;
else if (ArgFlags.isZExt())
LocInfo = CCValAssign::ZExt;
else
LocInfo = CCValAssign::AExt;
}
if (LocVT == MVT::i64) {
static const MCPhysReg RegList1[] = {
BPF::R1, BPF::R2, BPF::R3, BPF::R4, BPF::R5
};
if (unsigned Reg = State.AllocateReg(RegList1)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
unsigned Offset2 = State.AllocateStack(8, 8);
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
return false;
return true; // CC didn't match.
}
static bool RetCC_BPF32(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (LocVT == MVT::i32) {
if (unsigned Reg = State.AllocateReg(BPF::W0, BPF::R0)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
if (LocVT == MVT::i64) {
if (unsigned Reg = State.AllocateReg(BPF::R0, BPF::W0)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
return true; // CC didn't match.
}
static bool RetCC_BPF64(unsigned ValNo, MVT ValVT,
MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
if (LocVT == MVT::i64) {
if (unsigned Reg = State.AllocateReg(BPF::R0)) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
return true; // CC didn't match.
}
|