reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2314   extern const TargetRegisterClass HvxWRRegClass;

References

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2973     &Hexagon::HvxWRRegClass,

lib/Target/Hexagon/HexagonBitSimplify.cpp

 1619           FRC == &Hexagon::HvxWRRegClass) {

lib/Target/Hexagon/HexagonBitTracker.cpp

  119     for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
  150       return Hexagon::HvxWRRegClass;

lib/Target/Hexagon/HexagonCopyToCombine.cpp

  594     SuperRC = &Hexagon::HvxWRRegClass;
  871   } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {

lib/Target/Hexagon/HexagonISelLowering.cpp

 3037         return {0u, &Hexagon::HvxWRRegClass};
 3039         return {0u, &Hexagon::HvxWRRegClass};
 3214     return std::make_pair(&Hexagon::HvxWRRegClass, 1);

lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

   28     addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
   29     addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
   30     addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
   47     addRegisterClass(MVT::v256i8,  &Hexagon::HvxWRRegClass);
   48     addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
   49     addRegisterClass(MVT::v64i32,  &Hexagon::HvxWRRegClass);

lib/Target/Hexagon/HexagonInstrInfo.cpp

  851   if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
  932   } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
  991   } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {

lib/Target/Hexagon/HexagonRegisterInfo.cpp

  245   if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID())

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  871   if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass)