reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2299   extern const TargetRegisterClass PredRegsRegClass;

References

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 2958     &Hexagon::PredRegsRegClass,

lib/Target/Hexagon/HexagonBitSimplify.cpp

 1441   if (RC == &Hexagon::PredRegsRegClass) {
 2359       unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
 2368     Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);

lib/Target/Hexagon/HexagonBitTracker.cpp

  964         if (MRI.getRegClass(DefR) == &Hexagon::PredRegsRegClass) {

lib/Target/Hexagon/HexagonConstExtenders.cpp

 1926         MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass)

lib/Target/Hexagon/HexagonConstPropagation.cpp

 2357   if (Hexagon::PredRegsRegClass.hasSubClassEq(RC))
 2868       const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

  699   return RC == &Hexagon::PredRegsRegClass ||

lib/Target/Hexagon/HexagonGenPredicate.cpp

  139   return RC == &Hexagon::PredRegsRegClass;
  267   const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
  334         const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
  420   const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
  454   const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;

lib/Target/Hexagon/HexagonISelLowering.cpp

  289       Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
 1265   addRegisterClass(MVT::i1,    &Hexagon::PredRegsRegClass);
 1266   addRegisterClass(MVT::v2i1,  &Hexagon::PredRegsRegClass);  // bbbbaaaa
 1267   addRegisterClass(MVT::v4i1,  &Hexagon::PredRegsRegClass);  // ddccbbaa
 1268   addRegisterClass(MVT::v8i1,  &Hexagon::PredRegsRegClass);  // hgfedcba

lib/Target/Hexagon/HexagonInstrInfo.cpp

  804   if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
  828   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
  835       Hexagon::PredRegsRegClass.contains(DestReg)) {
  840   if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
  908   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
  971   } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
 1627       if (RC == &Hexagon::PredRegsRegClass) {
 1633       for (unsigned PR : Hexagon::PredRegsRegClass) {
 1987     TRC = &Hexagon::PredRegsRegClass;
 3310     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
 3321     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
 3346     if (Hexagon::PredRegsRegClass.contains(DstReg) &&
 3361     if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
 3830     if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
 3843     if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
 4010         Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
 4018     if (Hexagon::PredRegsRegClass.contains(DstReg) &&

lib/Target/Hexagon/HexagonSplitDouble.cpp

  503   assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  356   if (NewRC == &Hexagon::PredRegsRegClass) {
  455   if (RC == &Hexagon::PredRegsRegClass)
  708       if (predRegClass == &Hexagon::PredRegsRegClass)
  711     assert((predRegClass == &Hexagon::PredRegsRegClass) &&
  720       if (predRegClass == &Hexagon::PredRegsRegClass)
  723     assert((predRegClass == &Hexagon::PredRegsRegClass) &&
  875   if (RC == &Hexagon::PredRegsRegClass)
  878   if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
  948         Hexagon::PredRegsRegClass.contains(Op.getReg()))
  998             Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
 1018          Hexagon::PredRegsRegClass.contains(PReg1) &&
 1019          Hexagon::PredRegsRegClass.contains(PReg2) &&