gen/lib/Target/MSP430/MSP430GenInstrInfo.inc

reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace MSP430 {
  enum {
    PHI	= 0,
    INLINEASM	= 1,
    INLINEASM_BR	= 2,
    CFI_INSTRUCTION	= 3,
    EH_LABEL	= 4,
    GC_LABEL	= 5,
    ANNOTATION_LABEL	= 6,
    KILL	= 7,
    EXTRACT_SUBREG	= 8,
    INSERT_SUBREG	= 9,
    IMPLICIT_DEF	= 10,
    SUBREG_TO_REG	= 11,
    COPY_TO_REGCLASS	= 12,
    DBG_VALUE	= 13,
    DBG_LABEL	= 14,
    REG_SEQUENCE	= 15,
    COPY	= 16,
    BUNDLE	= 17,
    LIFETIME_START	= 18,
    LIFETIME_END	= 19,
    STACKMAP	= 20,
    FENTRY_CALL	= 21,
    PATCHPOINT	= 22,
    LOAD_STACK_GUARD	= 23,
    STATEPOINT	= 24,
    LOCAL_ESCAPE	= 25,
    FAULTING_OP	= 26,
    PATCHABLE_OP	= 27,
    PATCHABLE_FUNCTION_ENTER	= 28,
    PATCHABLE_RET	= 29,
    PATCHABLE_FUNCTION_EXIT	= 30,
    PATCHABLE_TAIL_CALL	= 31,
    PATCHABLE_EVENT_CALL	= 32,
    PATCHABLE_TYPED_EVENT_CALL	= 33,
    ICALL_BRANCH_FUNNEL	= 34,
    G_ADD	= 35,
    G_SUB	= 36,
    G_MUL	= 37,
    G_SDIV	= 38,
    G_UDIV	= 39,
    G_SREM	= 40,
    G_UREM	= 41,
    G_AND	= 42,
    G_OR	= 43,
    G_XOR	= 44,
    G_IMPLICIT_DEF	= 45,
    G_PHI	= 46,
    G_FRAME_INDEX	= 47,
    G_GLOBAL_VALUE	= 48,
    G_EXTRACT	= 49,
    G_UNMERGE_VALUES	= 50,
    G_INSERT	= 51,
    G_MERGE_VALUES	= 52,
    G_BUILD_VECTOR	= 53,
    G_BUILD_VECTOR_TRUNC	= 54,
    G_CONCAT_VECTORS	= 55,
    G_PTRTOINT	= 56,
    G_INTTOPTR	= 57,
    G_BITCAST	= 58,
    G_INTRINSIC_TRUNC	= 59,
    G_INTRINSIC_ROUND	= 60,
    G_LOAD	= 61,
    G_SEXTLOAD	= 62,
    G_ZEXTLOAD	= 63,
    G_INDEXED_LOAD	= 64,
    G_INDEXED_SEXTLOAD	= 65,
    G_INDEXED_ZEXTLOAD	= 66,
    G_STORE	= 67,
    G_INDEXED_STORE	= 68,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 69,
    G_ATOMIC_CMPXCHG	= 70,
    G_ATOMICRMW_XCHG	= 71,
    G_ATOMICRMW_ADD	= 72,
    G_ATOMICRMW_SUB	= 73,
    G_ATOMICRMW_AND	= 74,
    G_ATOMICRMW_NAND	= 75,
    G_ATOMICRMW_OR	= 76,
    G_ATOMICRMW_XOR	= 77,
    G_ATOMICRMW_MAX	= 78,
    G_ATOMICRMW_MIN	= 79,
    G_ATOMICRMW_UMAX	= 80,
    G_ATOMICRMW_UMIN	= 81,
    G_ATOMICRMW_FADD	= 82,
    G_ATOMICRMW_FSUB	= 83,
    G_FENCE	= 84,
    G_BRCOND	= 85,
    G_BRINDIRECT	= 86,
    G_INTRINSIC	= 87,
    G_INTRINSIC_W_SIDE_EFFECTS	= 88,
    G_ANYEXT	= 89,
    G_TRUNC	= 90,
    G_CONSTANT	= 91,
    G_FCONSTANT	= 92,
    G_VASTART	= 93,
    G_VAARG	= 94,
    G_SEXT	= 95,
    G_SEXT_INREG	= 96,
    G_ZEXT	= 97,
    G_SHL	= 98,
    G_LSHR	= 99,
    G_ASHR	= 100,
    G_ICMP	= 101,
    G_FCMP	= 102,
    G_SELECT	= 103,
    G_UADDO	= 104,
    G_UADDE	= 105,
    G_USUBO	= 106,
    G_USUBE	= 107,
    G_SADDO	= 108,
    G_SADDE	= 109,
    G_SSUBO	= 110,
    G_SSUBE	= 111,
    G_UMULO	= 112,
    G_SMULO	= 113,
    G_UMULH	= 114,
    G_SMULH	= 115,
    G_FADD	= 116,
    G_FSUB	= 117,
    G_FMUL	= 118,
    G_FMA	= 119,
    G_FMAD	= 120,
    G_FDIV	= 121,
    G_FREM	= 122,
    G_FPOW	= 123,
    G_FEXP	= 124,
    G_FEXP2	= 125,
    G_FLOG	= 126,
    G_FLOG2	= 127,
    G_FLOG10	= 128,
    G_FNEG	= 129,
    G_FPEXT	= 130,
    G_FPTRUNC	= 131,
    G_FPTOSI	= 132,
    G_FPTOUI	= 133,
    G_SITOFP	= 134,
    G_UITOFP	= 135,
    G_FABS	= 136,
    G_FCOPYSIGN	= 137,
    G_FCANONICALIZE	= 138,
    G_FMINNUM	= 139,
    G_FMAXNUM	= 140,
    G_FMINNUM_IEEE	= 141,
    G_FMAXNUM_IEEE	= 142,
    G_FMINIMUM	= 143,
    G_FMAXIMUM	= 144,
    G_GEP	= 145,
    G_PTR_MASK	= 146,
    G_SMIN	= 147,
    G_SMAX	= 148,
    G_UMIN	= 149,
    G_UMAX	= 150,
    G_BR	= 151,
    G_BRJT	= 152,
    G_INSERT_VECTOR_ELT	= 153,
    G_EXTRACT_VECTOR_ELT	= 154,
    G_SHUFFLE_VECTOR	= 155,
    G_CTTZ	= 156,
    G_CTTZ_ZERO_UNDEF	= 157,
    G_CTLZ	= 158,
    G_CTLZ_ZERO_UNDEF	= 159,
    G_CTPOP	= 160,
    G_BSWAP	= 161,
    G_BITREVERSE	= 162,
    G_FCEIL	= 163,
    G_FCOS	= 164,
    G_FSIN	= 165,
    G_FSQRT	= 166,
    G_FFLOOR	= 167,
    G_FRINT	= 168,
    G_FNEARBYINT	= 169,
    G_ADDRSPACE_CAST	= 170,
    G_BLOCK_ADDR	= 171,
    G_JUMP_TABLE	= 172,
    G_DYN_STACKALLOC	= 173,
    ADD16mc	= 174,
    ADD16mi	= 175,
    ADD16mm	= 176,
    ADD16mn	= 177,
    ADD16mp	= 178,
    ADD16mr	= 179,
    ADD16rc	= 180,
    ADD16ri	= 181,
    ADD16rm	= 182,
    ADD16rn	= 183,
    ADD16rp	= 184,
    ADD16rr	= 185,
    ADD8mc	= 186,
    ADD8mi	= 187,
    ADD8mm	= 188,
    ADD8mn	= 189,
    ADD8mp	= 190,
    ADD8mr	= 191,
    ADD8rc	= 192,
    ADD8ri	= 193,
    ADD8rm	= 194,
    ADD8rn	= 195,
    ADD8rp	= 196,
    ADD8rr	= 197,
    ADDC16mc	= 198,
    ADDC16mi	= 199,
    ADDC16mm	= 200,
    ADDC16mn	= 201,
    ADDC16mp	= 202,
    ADDC16mr	= 203,
    ADDC16rc	= 204,
    ADDC16ri	= 205,
    ADDC16rm	= 206,
    ADDC16rn	= 207,
    ADDC16rp	= 208,
    ADDC16rr	= 209,
    ADDC8mc	= 210,
    ADDC8mi	= 211,
    ADDC8mm	= 212,
    ADDC8mn	= 213,
    ADDC8mp	= 214,
    ADDC8mr	= 215,
    ADDC8rc	= 216,
    ADDC8ri	= 217,
    ADDC8rm	= 218,
    ADDC8rn	= 219,
    ADDC8rp	= 220,
    ADDC8rr	= 221,
    ADDframe	= 222,
    ADJCALLSTACKDOWN	= 223,
    ADJCALLSTACKUP	= 224,
    AND16mc	= 225,
    AND16mi	= 226,
    AND16mm	= 227,
    AND16mn	= 228,
    AND16mp	= 229,
    AND16mr	= 230,
    AND16rc	= 231,
    AND16ri	= 232,
    AND16rm	= 233,
    AND16rn	= 234,
    AND16rp	= 235,
    AND16rr	= 236,
    AND8mc	= 237,
    AND8mi	= 238,
    AND8mm	= 239,
    AND8mn	= 240,
    AND8mp	= 241,
    AND8mr	= 242,
    AND8rc	= 243,
    AND8ri	= 244,
    AND8rm	= 245,
    AND8rn	= 246,
    AND8rp	= 247,
    AND8rr	= 248,
    BIC16mc	= 249,
    BIC16mi	= 250,
    BIC16mm	= 251,
    BIC16mn	= 252,
    BIC16mp	= 253,
    BIC16mr	= 254,
    BIC16rc	= 255,
    BIC16ri	= 256,
    BIC16rm	= 257,
    BIC16rn	= 258,
    BIC16rp	= 259,
    BIC16rr	= 260,
    BIC8mc	= 261,
    BIC8mi	= 262,
    BIC8mm	= 263,
    BIC8mn	= 264,
    BIC8mp	= 265,
    BIC8mr	= 266,
    BIC8rc	= 267,
    BIC8ri	= 268,
    BIC8rm	= 269,
    BIC8rn	= 270,
    BIC8rp	= 271,
    BIC8rr	= 272,
    BIS16mc	= 273,
    BIS16mi	= 274,
    BIS16mm	= 275,
    BIS16mn	= 276,
    BIS16mp	= 277,
    BIS16mr	= 278,
    BIS16rc	= 279,
    BIS16ri	= 280,
    BIS16rm	= 281,
    BIS16rn	= 282,
    BIS16rp	= 283,
    BIS16rr	= 284,
    BIS8mc	= 285,
    BIS8mi	= 286,
    BIS8mm	= 287,
    BIS8mn	= 288,
    BIS8mp	= 289,
    BIS8mr	= 290,
    BIS8rc	= 291,
    BIS8ri	= 292,
    BIS8rm	= 293,
    BIS8rn	= 294,
    BIS8rp	= 295,
    BIS8rr	= 296,
    BIT16mc	= 297,
    BIT16mi	= 298,
    BIT16mm	= 299,
    BIT16mn	= 300,
    BIT16mp	= 301,
    BIT16mr	= 302,
    BIT16rc	= 303,
    BIT16ri	= 304,
    BIT16rm	= 305,
    BIT16rn	= 306,
    BIT16rp	= 307,
    BIT16rr	= 308,
    BIT8mc	= 309,
    BIT8mi	= 310,
    BIT8mm	= 311,
    BIT8mn	= 312,
    BIT8mp	= 313,
    BIT8mr	= 314,
    BIT8rc	= 315,
    BIT8ri	= 316,
    BIT8rm	= 317,
    BIT8rn	= 318,
    BIT8rp	= 319,
    BIT8rr	= 320,
    Bi	= 321,
    Bm	= 322,
    Br	= 323,
    CALLi	= 324,
    CALLm	= 325,
    CALLn	= 326,
    CALLp	= 327,
    CALLr	= 328,
    CMP16mc	= 329,
    CMP16mi	= 330,
    CMP16mm	= 331,
    CMP16mn	= 332,
    CMP16mp	= 333,
    CMP16mr	= 334,
    CMP16rc	= 335,
    CMP16ri	= 336,
    CMP16rm	= 337,
    CMP16rn	= 338,
    CMP16rp	= 339,
    CMP16rr	= 340,
    CMP8mc	= 341,
    CMP8mi	= 342,
    CMP8mm	= 343,
    CMP8mn	= 344,
    CMP8mp	= 345,
    CMP8mr	= 346,
    CMP8rc	= 347,
    CMP8ri	= 348,
    CMP8rm	= 349,
    CMP8rn	= 350,
    CMP8rp	= 351,
    CMP8rr	= 352,
    DADD16mc	= 353,
    DADD16mi	= 354,
    DADD16mm	= 355,
    DADD16mn	= 356,
    DADD16mp	= 357,
    DADD16mr	= 358,
    DADD16rc	= 359,
    DADD16ri	= 360,
    DADD16rm	= 361,
    DADD16rn	= 362,
    DADD16rp	= 363,
    DADD16rr	= 364,
    DADD8mc	= 365,
    DADD8mi	= 366,
    DADD8mm	= 367,
    DADD8mn	= 368,
    DADD8mp	= 369,
    DADD8mr	= 370,
    DADD8rc	= 371,
    DADD8ri	= 372,
    DADD8rm	= 373,
    DADD8rn	= 374,
    DADD8rp	= 375,
    DADD8rr	= 376,
    JCC	= 377,
    JMP	= 378,
    MOV16mc	= 379,
    MOV16mi	= 380,
    MOV16mm	= 381,
    MOV16mn	= 382,
    MOV16mr	= 383,
    MOV16rc	= 384,
    MOV16ri	= 385,
    MOV16rm	= 386,
    MOV16rn	= 387,
    MOV16rp	= 388,
    MOV16rr	= 389,
    MOV8mc	= 390,
    MOV8mi	= 391,
    MOV8mm	= 392,
    MOV8mn	= 393,
    MOV8mr	= 394,
    MOV8rc	= 395,
    MOV8ri	= 396,
    MOV8rm	= 397,
    MOV8rn	= 398,
    MOV8rp	= 399,
    MOV8rr	= 400,
    MOVZX16rm8	= 401,
    MOVZX16rr8	= 402,
    POP16r	= 403,
    PUSH16c	= 404,
    PUSH16i	= 405,
    PUSH16r	= 406,
    PUSH8r	= 407,
    RET	= 408,
    RETI	= 409,
    RRA16m	= 410,
    RRA16n	= 411,
    RRA16p	= 412,
    RRA16r	= 413,
    RRA8m	= 414,
    RRA8n	= 415,
    RRA8p	= 416,
    RRA8r	= 417,
    RRC16m	= 418,
    RRC16n	= 419,
    RRC16p	= 420,
    RRC16r	= 421,
    RRC8m	= 422,
    RRC8n	= 423,
    RRC8p	= 424,
    RRC8r	= 425,
    Rrcl16	= 426,
    Rrcl8	= 427,
    SEXT16m	= 428,
    SEXT16n	= 429,
    SEXT16p	= 430,
    SEXT16r	= 431,
    SUB16mc	= 432,
    SUB16mi	= 433,
    SUB16mm	= 434,
    SUB16mn	= 435,
    SUB16mp	= 436,
    SUB16mr	= 437,
    SUB16rc	= 438,
    SUB16ri	= 439,
    SUB16rm	= 440,
    SUB16rn	= 441,
    SUB16rp	= 442,
    SUB16rr	= 443,
    SUB8mc	= 444,
    SUB8mi	= 445,
    SUB8mm	= 446,
    SUB8mn	= 447,
    SUB8mp	= 448,
    SUB8mr	= 449,
    SUB8rc	= 450,
    SUB8ri	= 451,
    SUB8rm	= 452,
    SUB8rn	= 453,
    SUB8rp	= 454,
    SUB8rr	= 455,
    SUBC16mc	= 456,
    SUBC16mi	= 457,
    SUBC16mm	= 458,
    SUBC16mn	= 459,
    SUBC16mp	= 460,
    SUBC16mr	= 461,
    SUBC16rc	= 462,
    SUBC16ri	= 463,
    SUBC16rm	= 464,
    SUBC16rn	= 465,
    SUBC16rp	= 466,
    SUBC16rr	= 467,
    SUBC8mc	= 468,
    SUBC8mi	= 469,
    SUBC8mm	= 470,
    SUBC8mn	= 471,
    SUBC8mp	= 472,
    SUBC8mr	= 473,
    SUBC8rc	= 474,
    SUBC8ri	= 475,
    SUBC8rm	= 476,
    SUBC8rn	= 477,
    SUBC8rp	= 478,
    SUBC8rr	= 479,
    SWPB16m	= 480,
    SWPB16n	= 481,
    SWPB16p	= 482,
    SWPB16r	= 483,
    Select16	= 484,
    Select8	= 485,
    Shl16	= 486,
    Shl8	= 487,
    Sra16	= 488,
    Sra8	= 489,
    Srl16	= 490,
    Srl8	= 491,
    XOR16mc	= 492,
    XOR16mi	= 493,
    XOR16mm	= 494,
    XOR16mn	= 495,
    XOR16mp	= 496,
    XOR16mr	= 497,
    XOR16rc	= 498,
    XOR16ri	= 499,
    XOR16rm	= 500,
    XOR16rn	= 501,
    XOR16rp	= 502,
    XOR16rr	= 503,
    XOR8mc	= 504,
    XOR8mi	= 505,
    XOR8mm	= 506,
    XOR8mn	= 507,
    XOR8mp	= 508,
    XOR8mr	= 509,
    XOR8rc	= 510,
    XOR8ri	= 511,
    XOR8rm	= 512,
    XOR8rn	= 513,
    XOR8rp	= 514,
    XOR8rr	= 515,
    ZEXT16r	= 516,
    INSTRUCTION_LIST_END = 517
  };

} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace MSP430 {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static const MCPhysReg ImplicitList1[] = { MSP430::SR, 0 };
static const MCPhysReg ImplicitList2[] = { MSP430::SP, 0 };
static const MCPhysReg ImplicitList3[] = { MSP430::SP, MSP430::SR, 0 };
static const MCPhysReg ImplicitList4[] = { MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR, 0 };

static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo36[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo37[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo38[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo39[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo40[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo41[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo42[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo43[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo44[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo45[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo46[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo47[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo48[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo49[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo50[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo51[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo52[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo53[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo54[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo55[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo56[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo57[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo58[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo59[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo60[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo61[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo62[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo63[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo64[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo65[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo66[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo67[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo68[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo69[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo70[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo71[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo72[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo73[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
static const MCOperandInfo OperandInfo74[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo75[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo76[] = { { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo77[] = { { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };

extern const MCInstrDesc MSP430Insts[] = {
  { 0,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
  { 1,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
  { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  { 3,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
  { 4,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
  { 5,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
  { 6,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
  { 7,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
  { 8,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
  { 9,	4,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
  { 10,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
  { 11,	4,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
  { 12,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
  { 13,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
  { 14,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
  { 15,	2,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
  { 16,	2,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
  { 17,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
  { 18,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
  { 19,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
  { 20,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
  { 21,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
  { 22,	6,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
  { 23,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
  { 24,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
  { 25,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
  { 26,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
  { 27,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
  { 28,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
  { 29,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
  { 30,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
  { 31,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
  { 32,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
  { 33,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
  { 34,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
  { 35,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
  { 36,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
  { 37,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
  { 38,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
  { 39,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
  { 40,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
  { 41,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
  { 42,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
  { 43,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
  { 44,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
  { 45,	1,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
  { 46,	1,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
  { 47,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
  { 48,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
  { 49,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
  { 50,	2,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
  { 51,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
  { 52,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
  { 53,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
  { 54,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
  { 55,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
  { 56,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
  { 57,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
  { 58,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
  { 59,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
  { 60,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
  { 61,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
  { 62,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
  { 63,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
  { 64,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #64 = G_INDEXED_LOAD
  { 65,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_INDEXED_SEXTLOAD
  { 66,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #66 = G_INDEXED_ZEXTLOAD
  { 67,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #67 = G_STORE
  { 68,	5,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_INDEXED_STORE
  { 69,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
  { 70,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #70 = G_ATOMIC_CMPXCHG
  { 71,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_XCHG
  { 72,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_ADD
  { 73,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_SUB
  { 74,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_AND
  { 75,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_NAND
  { 76,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_OR
  { 77,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_XOR
  { 78,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #78 = G_ATOMICRMW_MAX
  { 79,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #79 = G_ATOMICRMW_MIN
  { 80,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #80 = G_ATOMICRMW_UMAX
  { 81,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #81 = G_ATOMICRMW_UMIN
  { 82,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #82 = G_ATOMICRMW_FADD
  { 83,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #83 = G_ATOMICRMW_FSUB
  { 84,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #84 = G_FENCE
  { 85,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_BRCOND
  { 86,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_BRINDIRECT
  { 87,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #87 = G_INTRINSIC
  { 88,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
  { 89,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ANYEXT
  { 90,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #90 = G_TRUNC
  { 91,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #91 = G_CONSTANT
  { 92,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #92 = G_FCONSTANT
  { 93,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #93 = G_VASTART
  { 94,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #94 = G_VAARG
  { 95,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_SEXT
  { 96,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #96 = G_SEXT_INREG
  { 97,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_ZEXT
  { 98,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #98 = G_SHL
  { 99,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #99 = G_LSHR
  { 100,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #100 = G_ASHR
  { 101,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #101 = G_ICMP
  { 102,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #102 = G_FCMP
  { 103,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #103 = G_SELECT
  { 104,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #104 = G_UADDO
  { 105,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #105 = G_UADDE
  { 106,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #106 = G_USUBO
  { 107,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #107 = G_USUBE
  { 108,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #108 = G_SADDO
  { 109,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #109 = G_SADDE
  { 110,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #110 = G_SSUBO
  { 111,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #111 = G_SSUBE
  { 112,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #112 = G_UMULO
  { 113,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #113 = G_SMULO
  { 114,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_UMULH
  { 115,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #115 = G_SMULH
  { 116,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #116 = G_FADD
  { 117,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #117 = G_FSUB
  { 118,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #118 = G_FMUL
  { 119,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #119 = G_FMA
  { 120,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #120 = G_FMAD
  { 121,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #121 = G_FDIV
  { 122,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #122 = G_FREM
  { 123,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #123 = G_FPOW
  { 124,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #124 = G_FEXP
  { 125,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #125 = G_FEXP2
  { 126,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #126 = G_FLOG
  { 127,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FLOG2
  { 128,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FLOG10
  { 129,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_FNEG
  { 130,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #130 = G_FPEXT
  { 131,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #131 = G_FPTRUNC
  { 132,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #132 = G_FPTOSI
  { 133,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #133 = G_FPTOUI
  { 134,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #134 = G_SITOFP
  { 135,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_UITOFP
  { 136,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #136 = G_FABS
  { 137,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #137 = G_FCOPYSIGN
  { 138,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #138 = G_FCANONICALIZE
  { 139,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #139 = G_FMINNUM
  { 140,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #140 = G_FMAXNUM
  { 141,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #141 = G_FMINNUM_IEEE
  { 142,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #142 = G_FMAXNUM_IEEE
  { 143,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #143 = G_FMINIMUM
  { 144,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #144 = G_FMAXIMUM
  { 145,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #145 = G_GEP
  { 146,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #146 = G_PTR_MASK
  { 147,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #147 = G_SMIN
  { 148,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #148 = G_SMAX
  { 149,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #149 = G_UMIN
  { 150,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #150 = G_UMAX
  { 151,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #151 = G_BR
  { 152,	3,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #152 = G_BRJT
  { 153,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #153 = G_INSERT_VECTOR_ELT
  { 154,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #154 = G_EXTRACT_VECTOR_ELT
  { 155,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #155 = G_SHUFFLE_VECTOR
  { 156,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #156 = G_CTTZ
  { 157,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #157 = G_CTTZ_ZERO_UNDEF
  { 158,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #158 = G_CTLZ
  { 159,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #159 = G_CTLZ_ZERO_UNDEF
  { 160,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #160 = G_CTPOP
  { 161,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #161 = G_BSWAP
  { 162,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #162 = G_BITREVERSE
  { 163,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #163 = G_FCEIL
  { 164,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #164 = G_FCOS
  { 165,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #165 = G_FSIN
  { 166,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #166 = G_FSQRT
  { 167,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #167 = G_FFLOOR
  { 168,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #168 = G_FRINT
  { 169,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #169 = G_FNEARBYINT
  { 170,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #170 = G_ADDRSPACE_CAST
  { 171,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #171 = G_BLOCK_ADDR
  { 172,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #172 = G_JUMP_TABLE
  { 173,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #173 = G_DYN_STACKALLOC
  { 174,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #174 = ADD16mc
  { 175,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #175 = ADD16mi
  { 176,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #176 = ADD16mm
  { 177,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #177 = ADD16mn
  { 178,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #178 = ADD16mp
  { 179,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #179 = ADD16mr
  { 180,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #180 = ADD16rc
  { 181,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #181 = ADD16ri
  { 182,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #182 = ADD16rm
  { 183,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #183 = ADD16rn
  { 184,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #184 = ADD16rp
  { 185,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #185 = ADD16rr
  { 186,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #186 = ADD8mc
  { 187,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #187 = ADD8mi
  { 188,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #188 = ADD8mm
  { 189,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #189 = ADD8mn
  { 190,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #190 = ADD8mp
  { 191,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #191 = ADD8mr
  { 192,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #192 = ADD8rc
  { 193,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #193 = ADD8ri
  { 194,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #194 = ADD8rm
  { 195,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #195 = ADD8rn
  { 196,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #196 = ADD8rp
  { 197,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #197 = ADD8rr
  { 198,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #198 = ADDC16mc
  { 199,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #199 = ADDC16mi
  { 200,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #200 = ADDC16mm
  { 201,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #201 = ADDC16mn
  { 202,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #202 = ADDC16mp
  { 203,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #203 = ADDC16mr
  { 204,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #204 = ADDC16rc
  { 205,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #205 = ADDC16ri
  { 206,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #206 = ADDC16rm
  { 207,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #207 = ADDC16rn
  { 208,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #208 = ADDC16rp
  { 209,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #209 = ADDC16rr
  { 210,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #210 = ADDC8mc
  { 211,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #211 = ADDC8mi
  { 212,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #212 = ADDC8mm
  { 213,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #213 = ADDC8mn
  { 214,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #214 = ADDC8mp
  { 215,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #215 = ADDC8mr
  { 216,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #216 = ADDC8rc
  { 217,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #217 = ADDC8ri
  { 218,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #218 = ADDC8rm
  { 219,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #219 = ADDC8rn
  { 220,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #220 = ADDC8rp
  { 221,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #221 = ADDC8rr
  { 222,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #222 = ADDframe
  { 223,	2,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #223 = ADJCALLSTACKDOWN
  { 224,	2,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo8, -1 ,nullptr },  // Inst #224 = ADJCALLSTACKUP
  { 225,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #225 = AND16mc
  { 226,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #226 = AND16mi
  { 227,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #227 = AND16mm
  { 228,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #228 = AND16mn
  { 229,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #229 = AND16mp
  { 230,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #230 = AND16mr
  { 231,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #231 = AND16rc
  { 232,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #232 = AND16ri
  { 233,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #233 = AND16rm
  { 234,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #234 = AND16rn
  { 235,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #235 = AND16rp
  { 236,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #236 = AND16rr
  { 237,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #237 = AND8mc
  { 238,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #238 = AND8mi
  { 239,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #239 = AND8mm
  { 240,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #240 = AND8mn
  { 241,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #241 = AND8mp
  { 242,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #242 = AND8mr
  { 243,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #243 = AND8rc
  { 244,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #244 = AND8ri
  { 245,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #245 = AND8rm
  { 246,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #246 = AND8rn
  { 247,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #247 = AND8rp
  { 248,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #248 = AND8rr
  { 249,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #249 = BIC16mc
  { 250,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #250 = BIC16mi
  { 251,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #251 = BIC16mm
  { 252,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #252 = BIC16mn
  { 253,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #253 = BIC16mp
  { 254,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #254 = BIC16mr
  { 255,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #255 = BIC16rc
  { 256,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #256 = BIC16ri
  { 257,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #257 = BIC16rm
  { 258,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #258 = BIC16rn
  { 259,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #259 = BIC16rp
  { 260,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #260 = BIC16rr
  { 261,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #261 = BIC8mc
  { 262,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #262 = BIC8mi
  { 263,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #263 = BIC8mm
  { 264,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #264 = BIC8mn
  { 265,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #265 = BIC8mp
  { 266,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #266 = BIC8mr
  { 267,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #267 = BIC8rc
  { 268,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #268 = BIC8ri
  { 269,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #269 = BIC8rm
  { 270,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #270 = BIC8rn
  { 271,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #271 = BIC8rp
  { 272,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #272 = BIC8rr
  { 273,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #273 = BIS16mc
  { 274,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #274 = BIS16mi
  { 275,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #275 = BIS16mm
  { 276,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #276 = BIS16mn
  { 277,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #277 = BIS16mp
  { 278,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #278 = BIS16mr
  { 279,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #279 = BIS16rc
  { 280,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #280 = BIS16ri
  { 281,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #281 = BIS16rm
  { 282,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #282 = BIS16rn
  { 283,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #283 = BIS16rp
  { 284,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #284 = BIS16rr
  { 285,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #285 = BIS8mc
  { 286,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #286 = BIS8mi
  { 287,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #287 = BIS8mm
  { 288,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #288 = BIS8mn
  { 289,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #289 = BIS8mp
  { 290,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #290 = BIS8mr
  { 291,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #291 = BIS8rc
  { 292,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #292 = BIS8ri
  { 293,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #293 = BIS8rm
  { 294,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #294 = BIS8rn
  { 295,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #295 = BIS8rp
  { 296,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #296 = BIS8rr
  { 297,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #297 = BIT16mc
  { 298,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #298 = BIT16mi
  { 299,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #299 = BIT16mm
  { 300,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #300 = BIT16mn
  { 301,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #301 = BIT16mp
  { 302,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #302 = BIT16mr
  { 303,	2,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #303 = BIT16rc
  { 304,	2,	0,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #304 = BIT16ri
  { 305,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #305 = BIT16rm
  { 306,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #306 = BIT16rn
  { 307,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #307 = BIT16rp
  { 308,	2,	0,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #308 = BIT16rr
  { 309,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #309 = BIT8mc
  { 310,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #310 = BIT8mi
  { 311,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #311 = BIT8mm
  { 312,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #312 = BIT8mn
  { 313,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #313 = BIT8mp
  { 314,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #314 = BIT8mr
  { 315,	2,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #315 = BIT8rc
  { 316,	2,	0,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #316 = BIT8ri
  { 317,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #317 = BIT8rm
  { 318,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #318 = BIT8rn
  { 319,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #319 = BIT8rp
  { 320,	2,	0,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo64, -1 ,nullptr },  // Inst #320 = BIT8rr
  { 321,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #321 = Bi
  { 322,	2,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #322 = Bm
  { 323,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #323 = Br
  { 324,	1,	0,	4,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo3, -1 ,nullptr },  // Inst #324 = CALLi
  { 325,	2,	0,	4,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo65, -1 ,nullptr },  // Inst #325 = CALLm
  { 326,	1,	0,	2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo67, -1 ,nullptr },  // Inst #326 = CALLn
  { 327,	1,	0,	2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo67, -1 ,nullptr },  // Inst #327 = CALLp
  { 328,	1,	0,	2,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList4, OperandInfo66, -1 ,nullptr },  // Inst #328 = CALLr
  { 329,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #329 = CMP16mc
  { 330,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #330 = CMP16mi
  { 331,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #331 = CMP16mm
  { 332,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #332 = CMP16mn
  { 333,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #333 = CMP16mp
  { 334,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #334 = CMP16mr
  { 335,	2,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #335 = CMP16rc
  { 336,	2,	0,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #336 = CMP16ri
  { 337,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #337 = CMP16rm
  { 338,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #338 = CMP16rn
  { 339,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #339 = CMP16rp
  { 340,	2,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #340 = CMP16rr
  { 341,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #341 = CMP8mc
  { 342,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #342 = CMP8mi
  { 343,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #343 = CMP8mm
  { 344,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #344 = CMP8mn
  { 345,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #345 = CMP8mp
  { 346,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #346 = CMP8mr
  { 347,	2,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #347 = CMP8rc
  { 348,	2,	0,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #348 = CMP8ri
  { 349,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #349 = CMP8rm
  { 350,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #350 = CMP8rn
  { 351,	2,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #351 = CMP8rp
  { 352,	2,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo64, -1 ,nullptr },  // Inst #352 = CMP8rr
  { 353,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #353 = DADD16mc
  { 354,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #354 = DADD16mi
  { 355,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #355 = DADD16mm
  { 356,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #356 = DADD16mn
  { 357,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #357 = DADD16mp
  { 358,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #358 = DADD16mr
  { 359,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #359 = DADD16rc
  { 360,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #360 = DADD16ri
  { 361,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #361 = DADD16rm
  { 362,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #362 = DADD16rn
  { 363,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #363 = DADD16rp
  { 364,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #364 = DADD16rr
  { 365,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #365 = DADD8mc
  { 366,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #366 = DADD8mi
  { 367,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #367 = DADD8mm
  { 368,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #368 = DADD8mn
  { 369,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #369 = DADD8mp
  { 370,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #370 = DADD8mr
  { 371,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #371 = DADD8rc
  { 372,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #372 = DADD8ri
  { 373,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #373 = DADD8rm
  { 374,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #374 = DADD8rn
  { 375,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #375 = DADD8rp
  { 376,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #376 = DADD8rr
  { 377,	2,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #377 = JCC
  { 378,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #378 = JMP
  { 379,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #379 = MOV16mc
  { 380,	3,	0,	6,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #380 = MOV16mi
  { 381,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #381 = MOV16mm
  { 382,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #382 = MOV16mn
  { 383,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #383 = MOV16mr
  { 384,	2,	1,	2,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #384 = MOV16rc
  { 385,	2,	1,	4,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #385 = MOV16ri
  { 386,	3,	1,	4,	0,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #386 = MOV16rm
  { 387,	2,	1,	2,	0,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #387 = MOV16rn
  { 388,	3,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #388 = MOV16rp
  { 389,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #389 = MOV16rr
  { 390,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #390 = MOV8mc
  { 391,	3,	0,	6,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #391 = MOV8mi
  { 392,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #392 = MOV8mm
  { 393,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #393 = MOV8mn
  { 394,	3,	0,	4,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #394 = MOV8mr
  { 395,	2,	1,	2,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #395 = MOV8rc
  { 396,	2,	1,	4,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #396 = MOV8ri
  { 397,	3,	1,	4,	0,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #397 = MOV8rm
  { 398,	2,	1,	2,	0,	0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #398 = MOV8rn
  { 399,	3,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #399 = MOV8rp
  { 400,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #400 = MOV8rr
  { 401,	3,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #401 = MOVZX16rm8
  { 402,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #402 = MOVZX16rr8
  { 403,	1,	1,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo66, -1 ,nullptr },  // Inst #403 = POP16r
  { 404,	1,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #404 = PUSH16c
  { 405,	1,	0,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo3, -1 ,nullptr },  // Inst #405 = PUSH16i
  { 406,	1,	0,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo66, -1 ,nullptr },  // Inst #406 = PUSH16r
  { 407,	1,	0,	2,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo71, -1 ,nullptr },  // Inst #407 = PUSH8r
  { 408,	0,	0,	2,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #408 = RET
  { 409,	0,	0,	2,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #409 = RETI
  { 410,	2,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #410 = RRA16m
  { 411,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #411 = RRA16n
  { 412,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #412 = RRA16p
  { 413,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #413 = RRA16r
  { 414,	2,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #414 = RRA8m
  { 415,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #415 = RRA8n
  { 416,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #416 = RRA8p
  { 417,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo73, -1 ,nullptr },  // Inst #417 = RRA8r
  { 418,	2,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #418 = RRC16m
  { 419,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #419 = RRC16n
  { 420,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #420 = RRC16p
  { 421,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #421 = RRC16r
  { 422,	2,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #422 = RRC8m
  { 423,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #423 = RRC8n
  { 424,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #424 = RRC8p
  { 425,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo73, -1 ,nullptr },  // Inst #425 = RRC8r
  { 426,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #426 = Rrcl16
  { 427,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo64, -1 ,nullptr },  // Inst #427 = Rrcl8
  { 428,	2,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #428 = SEXT16m
  { 429,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #429 = SEXT16n
  { 430,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #430 = SEXT16p
  { 431,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #431 = SEXT16r
  { 432,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #432 = SUB16mc
  { 433,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #433 = SUB16mi
  { 434,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #434 = SUB16mm
  { 435,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #435 = SUB16mn
  { 436,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #436 = SUB16mp
  { 437,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #437 = SUB16mr
  { 438,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #438 = SUB16rc
  { 439,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #439 = SUB16ri
  { 440,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #440 = SUB16rm
  { 441,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #441 = SUB16rn
  { 442,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #442 = SUB16rp
  { 443,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #443 = SUB16rr
  { 444,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #444 = SUB8mc
  { 445,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #445 = SUB8mi
  { 446,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #446 = SUB8mm
  { 447,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #447 = SUB8mn
  { 448,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #448 = SUB8mp
  { 449,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #449 = SUB8mr
  { 450,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #450 = SUB8rc
  { 451,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #451 = SUB8ri
  { 452,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #452 = SUB8rm
  { 453,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #453 = SUB8rn
  { 454,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #454 = SUB8rp
  { 455,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #455 = SUB8rr
  { 456,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #456 = SUBC16mc
  { 457,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #457 = SUBC16mi
  { 458,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #458 = SUBC16mm
  { 459,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #459 = SUBC16mn
  { 460,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #460 = SUBC16mp
  { 461,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #461 = SUBC16mr
  { 462,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #462 = SUBC16rc
  { 463,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #463 = SUBC16ri
  { 464,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #464 = SUBC16rm
  { 465,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #465 = SUBC16rn
  { 466,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #466 = SUBC16rp
  { 467,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #467 = SUBC16rr
  { 468,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #468 = SUBC8mc
  { 469,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #469 = SUBC8mi
  { 470,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #470 = SUBC8mm
  { 471,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #471 = SUBC8mn
  { 472,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #472 = SUBC8mp
  { 473,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #473 = SUBC8mr
  { 474,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #474 = SUBC8rc
  { 475,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #475 = SUBC8ri
  { 476,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #476 = SUBC8rm
  { 477,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #477 = SUBC8rn
  { 478,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #478 = SUBC8rp
  { 479,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #479 = SUBC8rr
  { 480,	2,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #480 = SWPB16m
  { 481,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #481 = SWPB16n
  { 482,	1,	0,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #482 = SWPB16p
  { 483,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #483 = SWPB16r
  { 484,	4,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #484 = Select16
  { 485,	4,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #485 = Select8
  { 486,	3,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr },  // Inst #486 = Shl16
  { 487,	3,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr },  // Inst #487 = Shl8
  { 488,	3,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr },  // Inst #488 = Sra16
  { 489,	3,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr },  // Inst #489 = Sra8
  { 490,	3,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr },  // Inst #490 = Srl16
  { 491,	3,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr },  // Inst #491 = Srl8
  { 492,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #492 = XOR16mc
  { 493,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #493 = XOR16mi
  { 494,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #494 = XOR16mm
  { 495,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #495 = XOR16mn
  { 496,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #496 = XOR16mp
  { 497,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #497 = XOR16mr
  { 498,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #498 = XOR16rc
  { 499,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #499 = XOR16ri
  { 500,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #500 = XOR16rm
  { 501,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #501 = XOR16rn
  { 502,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #502 = XOR16rp
  { 503,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #503 = XOR16rr
  { 504,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #504 = XOR8mc
  { 505,	3,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #505 = XOR8mi
  { 506,	4,	0,	6,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #506 = XOR8mm
  { 507,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #507 = XOR8mn
  { 508,	3,	0,	4,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #508 = XOR8mp
  { 509,	3,	0,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr },  // Inst #509 = XOR8mr
  { 510,	3,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr },  // Inst #510 = XOR8rc
  { 511,	3,	1,	4,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #511 = XOR8ri
  { 512,	4,	1,	4,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo50, -1 ,nullptr },  // Inst #512 = XOR8rm
  { 513,	3,	1,	2,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo51, -1 ,nullptr },  // Inst #513 = XOR8rn
  { 514,	4,	2,	2,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #514 = XOR8rp
  { 515,	3,	1,	2,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #515 = XOR8rr
  { 516,	2,	1,	2,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #516 = ZEXT16r
};

extern const char MSP430InstrNameData[] = {
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
  /* 9 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
  /* 17 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
  /* 25 */ 'S', 'r', 'a', '1', '6', 0,
  /* 31 */ 'R', 'r', 'c', 'l', '1', '6', 0,
  /* 38 */ 'S', 'h', 'l', '1', '6', 0,
  /* 44 */ 'S', 'r', 'l', '1', '6', 0,
  /* 50 */ 'S', 'e', 'l', 'e', 'c', 't', '1', '6', 0,
  /* 59 */ 'S', 'r', 'a', '8', 0,
  /* 64 */ 'R', 'r', 'c', 'l', '8', 0,
  /* 70 */ 'S', 'h', 'l', '8', 0,
  /* 75 */ 'S', 'r', 'l', '8', 0,
  /* 80 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'm', '8', 0,
  /* 91 */ 'M', 'O', 'V', 'Z', 'X', '1', '6', 'r', 'r', '8', 0,
  /* 102 */ 'S', 'e', 'l', 'e', 'c', 't', '8', 0,
  /* 110 */ 'G', '_', 'F', 'M', 'A', 0,
  /* 116 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
  /* 123 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'S', 'U', 'B', 0,
  /* 140 */ 'G', '_', 'S', 'U', 'B', 0,
  /* 146 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
  /* 162 */ 'J', 'C', 'C', 0,
  /* 166 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
  /* 178 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
  /* 188 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 206 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 214 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 235 */ 'G', '_', 'D', 'Y', 'N', '_', 'S', 'T', 'A', 'C', 'K', 'A', 'L', 'L', 'O', 'C', 0,
  /* 252 */ 'G', '_', 'F', 'M', 'A', 'D', 0,
  /* 259 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 278 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 289 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 308 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 319 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'L', 'O', 'A', 'D', 0,
  /* 334 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
  /* 341 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
  /* 348 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'A', 'D', 'D', 0,
  /* 365 */ 'G', '_', 'A', 'D', 'D', 0,
  /* 371 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
  /* 387 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
  /* 404 */ 'G', '_', 'A', 'N', 'D', 0,
  /* 410 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
  /* 426 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
  /* 439 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
  /* 448 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
  /* 466 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
  /* 483 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
  /* 491 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
  /* 499 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0,
  /* 507 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
  /* 520 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
  /* 528 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
  /* 536 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
  /* 551 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
  /* 566 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0,
  /* 579 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
  /* 586 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
  /* 599 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'T', 'O', 'R', 'E', 0,
  /* 615 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
  /* 623 */ 'G', '_', 'B', 'I', 'T', 'R', 'E', 'V', 'E', 'R', 'S', 'E', 0,
  /* 636 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
  /* 646 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
  /* 661 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
  /* 677 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
  /* 695 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
  /* 713 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
  /* 728 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
  /* 735 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
  /* 750 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
  /* 764 */ 'G', '_', 'S', 'E', 'X', 'T', '_', 'I', 'N', 'R', 'E', 'G', 0,
  /* 777 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
  /* 791 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
  /* 808 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
  /* 825 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
  /* 832 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
  /* 840 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
  /* 848 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
  /* 856 */ 'G', '_', 'P', 'H', 'I', 0,
  /* 862 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
  /* 871 */ 'R', 'E', 'T', 'I', 0,
  /* 876 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
  /* 885 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
  /* 896 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 905 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 915 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 924 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 941 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
  /* 961 */ 'G', '_', 'S', 'H', 'L', 0,
  /* 967 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
  /* 975 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
  /* 995 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 1022 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 1043 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
  /* 1055 */ 'K', 'I', 'L', 'L', 0,
  /* 1060 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
  /* 1067 */ 'G', '_', 'M', 'U', 'L', 0,
  /* 1073 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
  /* 1080 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
  /* 1087 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
  /* 1094 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
  /* 1104 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0,
  /* 1115 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0,
  /* 1126 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0,
  /* 1136 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0,
  /* 1146 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0,
  /* 1158 */ 'G', '_', 'S', 'M', 'I', 'N', 0,
  /* 1165 */ 'G', '_', 'U', 'M', 'I', 'N', 0,
  /* 1172 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
  /* 1189 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
  /* 1205 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
  /* 1212 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
  /* 1228 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
  /* 1245 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
  /* 1253 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
  /* 1261 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
  /* 1269 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
  /* 1277 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
  /* 1285 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
  /* 1293 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
  /* 1302 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
  /* 1310 */ 'G', '_', 'G', 'E', 'P', 0,
  /* 1316 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
  /* 1325 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
  /* 1334 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
  /* 1341 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
  /* 1348 */ 'J', 'M', 'P', 0,
  /* 1352 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
  /* 1360 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
  /* 1373 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
  /* 1385 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
  /* 1400 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
  /* 1407 */ 'G', '_', 'B', 'R', 0,
  /* 1412 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
  /* 1425 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
  /* 1438 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
  /* 1463 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
  /* 1470 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
  /* 1477 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
  /* 1486 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
  /* 1501 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
  /* 1518 */ 'G', '_', 'X', 'O', 'R', 0,
  /* 1524 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
  /* 1540 */ 'G', '_', 'O', 'R', 0,
  /* 1545 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
  /* 1560 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
  /* 1571 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
  /* 1578 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
  /* 1595 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
  /* 1610 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
  /* 1617 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
  /* 1634 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
  /* 1651 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
  /* 1681 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
  /* 1708 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
  /* 1718 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
  /* 1727 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
  /* 1740 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
  /* 1754 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
  /* 1778 */ 'G', '_', 'B', 'R', 'J', 'T', 0,
  /* 1785 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
  /* 1806 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
  /* 1826 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
  /* 1838 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
  /* 1849 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
  /* 1860 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
  /* 1871 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
  /* 1882 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0,
  /* 1890 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0,
  /* 1903 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
  /* 1913 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
  /* 1928 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
  /* 1937 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
  /* 1945 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
  /* 1955 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
  /* 1972 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
  /* 1980 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
  /* 1987 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
  /* 1996 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
  /* 2003 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
  /* 2010 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
  /* 2017 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
  /* 2024 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
  /* 2031 */ 'G', '_', 'S', 'M', 'A', 'X', 0,
  /* 2038 */ 'G', '_', 'U', 'M', 'A', 'X', 0,
  /* 2045 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
  /* 2062 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
  /* 2078 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
  /* 2092 */ 'C', 'O', 'P', 'Y', 0,
  /* 2097 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
  /* 2104 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
  /* 2111 */ 'P', 'U', 'S', 'H', '1', '6', 'c', 0,
  /* 2119 */ 'S', 'U', 'B', '1', '6', 'm', 'c', 0,
  /* 2127 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'c', 0,
  /* 2136 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'c', 0,
  /* 2145 */ 'B', 'I', 'C', '1', '6', 'm', 'c', 0,
  /* 2153 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'c', 0,
  /* 2162 */ 'A', 'N', 'D', '1', '6', 'm', 'c', 0,
  /* 2170 */ 'C', 'M', 'P', '1', '6', 'm', 'c', 0,
  /* 2178 */ 'X', 'O', 'R', '1', '6', 'm', 'c', 0,
  /* 2186 */ 'B', 'I', 'S', '1', '6', 'm', 'c', 0,
  /* 2194 */ 'B', 'I', 'T', '1', '6', 'm', 'c', 0,
  /* 2202 */ 'M', 'O', 'V', '1', '6', 'm', 'c', 0,
  /* 2210 */ 'S', 'U', 'B', '8', 'm', 'c', 0,
  /* 2217 */ 'S', 'U', 'B', 'C', '8', 'm', 'c', 0,
  /* 2225 */ 'A', 'D', 'D', 'C', '8', 'm', 'c', 0,
  /* 2233 */ 'B', 'I', 'C', '8', 'm', 'c', 0,
  /* 2240 */ 'D', 'A', 'D', 'D', '8', 'm', 'c', 0,
  /* 2248 */ 'A', 'N', 'D', '8', 'm', 'c', 0,
  /* 2255 */ 'C', 'M', 'P', '8', 'm', 'c', 0,
  /* 2262 */ 'X', 'O', 'R', '8', 'm', 'c', 0,
  /* 2269 */ 'B', 'I', 'S', '8', 'm', 'c', 0,
  /* 2276 */ 'B', 'I', 'T', '8', 'm', 'c', 0,
  /* 2283 */ 'M', 'O', 'V', '8', 'm', 'c', 0,
  /* 2290 */ 'S', 'U', 'B', '1', '6', 'r', 'c', 0,
  /* 2298 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'c', 0,
  /* 2307 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'c', 0,
  /* 2316 */ 'B', 'I', 'C', '1', '6', 'r', 'c', 0,
  /* 2324 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'c', 0,
  /* 2333 */ 'A', 'N', 'D', '1', '6', 'r', 'c', 0,
  /* 2341 */ 'C', 'M', 'P', '1', '6', 'r', 'c', 0,
  /* 2349 */ 'X', 'O', 'R', '1', '6', 'r', 'c', 0,
  /* 2357 */ 'B', 'I', 'S', '1', '6', 'r', 'c', 0,
  /* 2365 */ 'B', 'I', 'T', '1', '6', 'r', 'c', 0,
  /* 2373 */ 'M', 'O', 'V', '1', '6', 'r', 'c', 0,
  /* 2381 */ 'S', 'U', 'B', '8', 'r', 'c', 0,
  /* 2388 */ 'S', 'U', 'B', 'C', '8', 'r', 'c', 0,
  /* 2396 */ 'A', 'D', 'D', 'C', '8', 'r', 'c', 0,
  /* 2404 */ 'B', 'I', 'C', '8', 'r', 'c', 0,
  /* 2411 */ 'D', 'A', 'D', 'D', '8', 'r', 'c', 0,
  /* 2419 */ 'A', 'N', 'D', '8', 'r', 'c', 0,
  /* 2426 */ 'C', 'M', 'P', '8', 'r', 'c', 0,
  /* 2433 */ 'X', 'O', 'R', '8', 'r', 'c', 0,
  /* 2440 */ 'B', 'I', 'S', '8', 'r', 'c', 0,
  /* 2447 */ 'B', 'I', 'T', '8', 'r', 'c', 0,
  /* 2454 */ 'M', 'O', 'V', '8', 'r', 'c', 0,
  /* 2461 */ 'A', 'D', 'D', 'f', 'r', 'a', 'm', 'e', 0,
  /* 2470 */ 'P', 'U', 'S', 'H', '1', '6', 'i', 0,
  /* 2478 */ 'B', 'i', 0,
  /* 2481 */ 'C', 'A', 'L', 'L', 'i', 0,
  /* 2487 */ 'S', 'U', 'B', '1', '6', 'm', 'i', 0,
  /* 2495 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'i', 0,
  /* 2504 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'i', 0,
  /* 2513 */ 'B', 'I', 'C', '1', '6', 'm', 'i', 0,
  /* 2521 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'i', 0,
  /* 2530 */ 'A', 'N', 'D', '1', '6', 'm', 'i', 0,
  /* 2538 */ 'C', 'M', 'P', '1', '6', 'm', 'i', 0,
  /* 2546 */ 'X', 'O', 'R', '1', '6', 'm', 'i', 0,
  /* 2554 */ 'B', 'I', 'S', '1', '6', 'm', 'i', 0,
  /* 2562 */ 'B', 'I', 'T', '1', '6', 'm', 'i', 0,
  /* 2570 */ 'M', 'O', 'V', '1', '6', 'm', 'i', 0,
  /* 2578 */ 'S', 'U', 'B', '8', 'm', 'i', 0,
  /* 2585 */ 'S', 'U', 'B', 'C', '8', 'm', 'i', 0,
  /* 2593 */ 'A', 'D', 'D', 'C', '8', 'm', 'i', 0,
  /* 2601 */ 'B', 'I', 'C', '8', 'm', 'i', 0,
  /* 2608 */ 'D', 'A', 'D', 'D', '8', 'm', 'i', 0,
  /* 2616 */ 'A', 'N', 'D', '8', 'm', 'i', 0,
  /* 2623 */ 'C', 'M', 'P', '8', 'm', 'i', 0,
  /* 2630 */ 'X', 'O', 'R', '8', 'm', 'i', 0,
  /* 2637 */ 'B', 'I', 'S', '8', 'm', 'i', 0,
  /* 2644 */ 'B', 'I', 'T', '8', 'm', 'i', 0,
  /* 2651 */ 'M', 'O', 'V', '8', 'm', 'i', 0,
  /* 2658 */ 'S', 'U', 'B', '1', '6', 'r', 'i', 0,
  /* 2666 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'i', 0,
  /* 2675 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'i', 0,
  /* 2684 */ 'B', 'I', 'C', '1', '6', 'r', 'i', 0,
  /* 2692 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'i', 0,
  /* 2701 */ 'A', 'N', 'D', '1', '6', 'r', 'i', 0,
  /* 2709 */ 'C', 'M', 'P', '1', '6', 'r', 'i', 0,
  /* 2717 */ 'X', 'O', 'R', '1', '6', 'r', 'i', 0,
  /* 2725 */ 'B', 'I', 'S', '1', '6', 'r', 'i', 0,
  /* 2733 */ 'B', 'I', 'T', '1', '6', 'r', 'i', 0,
  /* 2741 */ 'M', 'O', 'V', '1', '6', 'r', 'i', 0,
  /* 2749 */ 'S', 'U', 'B', '8', 'r', 'i', 0,
  /* 2756 */ 'S', 'U', 'B', 'C', '8', 'r', 'i', 0,
  /* 2764 */ 'A', 'D', 'D', 'C', '8', 'r', 'i', 0,
  /* 2772 */ 'B', 'I', 'C', '8', 'r', 'i', 0,
  /* 2779 */ 'D', 'A', 'D', 'D', '8', 'r', 'i', 0,
  /* 2787 */ 'A', 'N', 'D', '8', 'r', 'i', 0,
  /* 2794 */ 'C', 'M', 'P', '8', 'r', 'i', 0,
  /* 2801 */ 'X', 'O', 'R', '8', 'r', 'i', 0,
  /* 2808 */ 'B', 'I', 'S', '8', 'r', 'i', 0,
  /* 2815 */ 'B', 'I', 'T', '8', 'r', 'i', 0,
  /* 2822 */ 'M', 'O', 'V', '8', 'r', 'i', 0,
  /* 2829 */ 'R', 'R', 'A', '1', '6', 'm', 0,
  /* 2836 */ 'S', 'W', 'P', 'B', '1', '6', 'm', 0,
  /* 2844 */ 'R', 'R', 'C', '1', '6', 'm', 0,
  /* 2851 */ 'S', 'E', 'X', 'T', '1', '6', 'm', 0,
  /* 2859 */ 'R', 'R', 'A', '8', 'm', 0,
  /* 2865 */ 'R', 'R', 'C', '8', 'm', 0,
  /* 2871 */ 'B', 'm', 0,
  /* 2874 */ 'C', 'A', 'L', 'L', 'm', 0,
  /* 2880 */ 'S', 'U', 'B', '1', '6', 'm', 'm', 0,
  /* 2888 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'm', 0,
  /* 2897 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'm', 0,
  /* 2906 */ 'B', 'I', 'C', '1', '6', 'm', 'm', 0,
  /* 2914 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'm', 0,
  /* 2923 */ 'A', 'N', 'D', '1', '6', 'm', 'm', 0,
  /* 2931 */ 'C', 'M', 'P', '1', '6', 'm', 'm', 0,
  /* 2939 */ 'X', 'O', 'R', '1', '6', 'm', 'm', 0,
  /* 2947 */ 'B', 'I', 'S', '1', '6', 'm', 'm', 0,
  /* 2955 */ 'B', 'I', 'T', '1', '6', 'm', 'm', 0,
  /* 2963 */ 'M', 'O', 'V', '1', '6', 'm', 'm', 0,
  /* 2971 */ 'S', 'U', 'B', '8', 'm', 'm', 0,
  /* 2978 */ 'S', 'U', 'B', 'C', '8', 'm', 'm', 0,
  /* 2986 */ 'A', 'D', 'D', 'C', '8', 'm', 'm', 0,
  /* 2994 */ 'B', 'I', 'C', '8', 'm', 'm', 0,
  /* 3001 */ 'D', 'A', 'D', 'D', '8', 'm', 'm', 0,
  /* 3009 */ 'A', 'N', 'D', '8', 'm', 'm', 0,
  /* 3016 */ 'C', 'M', 'P', '8', 'm', 'm', 0,
  /* 3023 */ 'X', 'O', 'R', '8', 'm', 'm', 0,
  /* 3030 */ 'B', 'I', 'S', '8', 'm', 'm', 0,
  /* 3037 */ 'B', 'I', 'T', '8', 'm', 'm', 0,
  /* 3044 */ 'M', 'O', 'V', '8', 'm', 'm', 0,
  /* 3051 */ 'S', 'U', 'B', '1', '6', 'r', 'm', 0,
  /* 3059 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'm', 0,
  /* 3068 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'm', 0,
  /* 3077 */ 'B', 'I', 'C', '1', '6', 'r', 'm', 0,
  /* 3085 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'm', 0,
  /* 3094 */ 'A', 'N', 'D', '1', '6', 'r', 'm', 0,
  /* 3102 */ 'C', 'M', 'P', '1', '6', 'r', 'm', 0,
  /* 3110 */ 'X', 'O', 'R', '1', '6', 'r', 'm', 0,
  /* 3118 */ 'B', 'I', 'S', '1', '6', 'r', 'm', 0,
  /* 3126 */ 'B', 'I', 'T', '1', '6', 'r', 'm', 0,
  /* 3134 */ 'M', 'O', 'V', '1', '6', 'r', 'm', 0,
  /* 3142 */ 'S', 'U', 'B', '8', 'r', 'm', 0,
  /* 3149 */ 'S', 'U', 'B', 'C', '8', 'r', 'm', 0,
  /* 3157 */ 'A', 'D', 'D', 'C', '8', 'r', 'm', 0,
  /* 3165 */ 'B', 'I', 'C', '8', 'r', 'm', 0,
  /* 3172 */ 'D', 'A', 'D', 'D', '8', 'r', 'm', 0,
  /* 3180 */ 'A', 'N', 'D', '8', 'r', 'm', 0,
  /* 3187 */ 'C', 'M', 'P', '8', 'r', 'm', 0,
  /* 3194 */ 'X', 'O', 'R', '8', 'r', 'm', 0,
  /* 3201 */ 'B', 'I', 'S', '8', 'r', 'm', 0,
  /* 3208 */ 'B', 'I', 'T', '8', 'r', 'm', 0,
  /* 3215 */ 'M', 'O', 'V', '8', 'r', 'm', 0,
  /* 3222 */ 'R', 'R', 'A', '1', '6', 'n', 0,
  /* 3229 */ 'S', 'W', 'P', 'B', '1', '6', 'n', 0,
  /* 3237 */ 'R', 'R', 'C', '1', '6', 'n', 0,
  /* 3244 */ 'S', 'E', 'X', 'T', '1', '6', 'n', 0,
  /* 3252 */ 'R', 'R', 'A', '8', 'n', 0,
  /* 3258 */ 'R', 'R', 'C', '8', 'n', 0,
  /* 3264 */ 'C', 'A', 'L', 'L', 'n', 0,
  /* 3270 */ 'S', 'U', 'B', '1', '6', 'm', 'n', 0,
  /* 3278 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'n', 0,
  /* 3287 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'n', 0,
  /* 3296 */ 'B', 'I', 'C', '1', '6', 'm', 'n', 0,
  /* 3304 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'n', 0,
  /* 3313 */ 'A', 'N', 'D', '1', '6', 'm', 'n', 0,
  /* 3321 */ 'C', 'M', 'P', '1', '6', 'm', 'n', 0,
  /* 3329 */ 'X', 'O', 'R', '1', '6', 'm', 'n', 0,
  /* 3337 */ 'B', 'I', 'S', '1', '6', 'm', 'n', 0,
  /* 3345 */ 'B', 'I', 'T', '1', '6', 'm', 'n', 0,
  /* 3353 */ 'M', 'O', 'V', '1', '6', 'm', 'n', 0,
  /* 3361 */ 'S', 'U', 'B', '8', 'm', 'n', 0,
  /* 3368 */ 'S', 'U', 'B', 'C', '8', 'm', 'n', 0,
  /* 3376 */ 'A', 'D', 'D', 'C', '8', 'm', 'n', 0,
  /* 3384 */ 'B', 'I', 'C', '8', 'm', 'n', 0,
  /* 3391 */ 'D', 'A', 'D', 'D', '8', 'm', 'n', 0,
  /* 3399 */ 'A', 'N', 'D', '8', 'm', 'n', 0,
  /* 3406 */ 'C', 'M', 'P', '8', 'm', 'n', 0,
  /* 3413 */ 'X', 'O', 'R', '8', 'm', 'n', 0,
  /* 3420 */ 'B', 'I', 'S', '8', 'm', 'n', 0,
  /* 3427 */ 'B', 'I', 'T', '8', 'm', 'n', 0,
  /* 3434 */ 'M', 'O', 'V', '8', 'm', 'n', 0,
  /* 3441 */ 'S', 'U', 'B', '1', '6', 'r', 'n', 0,
  /* 3449 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'n', 0,
  /* 3458 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'n', 0,
  /* 3467 */ 'B', 'I', 'C', '1', '6', 'r', 'n', 0,
  /* 3475 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'n', 0,
  /* 3484 */ 'A', 'N', 'D', '1', '6', 'r', 'n', 0,
  /* 3492 */ 'C', 'M', 'P', '1', '6', 'r', 'n', 0,
  /* 3500 */ 'X', 'O', 'R', '1', '6', 'r', 'n', 0,
  /* 3508 */ 'B', 'I', 'S', '1', '6', 'r', 'n', 0,
  /* 3516 */ 'B', 'I', 'T', '1', '6', 'r', 'n', 0,
  /* 3524 */ 'M', 'O', 'V', '1', '6', 'r', 'n', 0,
  /* 3532 */ 'S', 'U', 'B', '8', 'r', 'n', 0,
  /* 3539 */ 'S', 'U', 'B', 'C', '8', 'r', 'n', 0,
  /* 3547 */ 'A', 'D', 'D', 'C', '8', 'r', 'n', 0,
  /* 3555 */ 'B', 'I', 'C', '8', 'r', 'n', 0,
  /* 3562 */ 'D', 'A', 'D', 'D', '8', 'r', 'n', 0,
  /* 3570 */ 'A', 'N', 'D', '8', 'r', 'n', 0,
  /* 3577 */ 'C', 'M', 'P', '8', 'r', 'n', 0,
  /* 3584 */ 'X', 'O', 'R', '8', 'r', 'n', 0,
  /* 3591 */ 'B', 'I', 'S', '8', 'r', 'n', 0,
  /* 3598 */ 'B', 'I', 'T', '8', 'r', 'n', 0,
  /* 3605 */ 'M', 'O', 'V', '8', 'r', 'n', 0,
  /* 3612 */ 'R', 'R', 'A', '1', '6', 'p', 0,
  /* 3619 */ 'S', 'W', 'P', 'B', '1', '6', 'p', 0,
  /* 3627 */ 'R', 'R', 'C', '1', '6', 'p', 0,
  /* 3634 */ 'S', 'E', 'X', 'T', '1', '6', 'p', 0,
  /* 3642 */ 'R', 'R', 'A', '8', 'p', 0,
  /* 3648 */ 'R', 'R', 'C', '8', 'p', 0,
  /* 3654 */ 'C', 'A', 'L', 'L', 'p', 0,
  /* 3660 */ 'S', 'U', 'B', '1', '6', 'm', 'p', 0,
  /* 3668 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'p', 0,
  /* 3677 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'p', 0,
  /* 3686 */ 'B', 'I', 'C', '1', '6', 'm', 'p', 0,
  /* 3694 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'p', 0,
  /* 3703 */ 'A', 'N', 'D', '1', '6', 'm', 'p', 0,
  /* 3711 */ 'C', 'M', 'P', '1', '6', 'm', 'p', 0,
  /* 3719 */ 'X', 'O', 'R', '1', '6', 'm', 'p', 0,
  /* 3727 */ 'B', 'I', 'S', '1', '6', 'm', 'p', 0,
  /* 3735 */ 'B', 'I', 'T', '1', '6', 'm', 'p', 0,
  /* 3743 */ 'S', 'U', 'B', '8', 'm', 'p', 0,
  /* 3750 */ 'S', 'U', 'B', 'C', '8', 'm', 'p', 0,
  /* 3758 */ 'A', 'D', 'D', 'C', '8', 'm', 'p', 0,
  /* 3766 */ 'B', 'I', 'C', '8', 'm', 'p', 0,
  /* 3773 */ 'D', 'A', 'D', 'D', '8', 'm', 'p', 0,
  /* 3781 */ 'A', 'N', 'D', '8', 'm', 'p', 0,
  /* 3788 */ 'C', 'M', 'P', '8', 'm', 'p', 0,
  /* 3795 */ 'X', 'O', 'R', '8', 'm', 'p', 0,
  /* 3802 */ 'B', 'I', 'S', '8', 'm', 'p', 0,
  /* 3809 */ 'B', 'I', 'T', '8', 'm', 'p', 0,
  /* 3816 */ 'S', 'U', 'B', '1', '6', 'r', 'p', 0,
  /* 3824 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'p', 0,
  /* 3833 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'p', 0,
  /* 3842 */ 'B', 'I', 'C', '1', '6', 'r', 'p', 0,
  /* 3850 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'p', 0,
  /* 3859 */ 'A', 'N', 'D', '1', '6', 'r', 'p', 0,
  /* 3867 */ 'C', 'M', 'P', '1', '6', 'r', 'p', 0,
  /* 3875 */ 'X', 'O', 'R', '1', '6', 'r', 'p', 0,
  /* 3883 */ 'B', 'I', 'S', '1', '6', 'r', 'p', 0,
  /* 3891 */ 'B', 'I', 'T', '1', '6', 'r', 'p', 0,
  /* 3899 */ 'M', 'O', 'V', '1', '6', 'r', 'p', 0,
  /* 3907 */ 'S', 'U', 'B', '8', 'r', 'p', 0,
  /* 3914 */ 'S', 'U', 'B', 'C', '8', 'r', 'p', 0,
  /* 3922 */ 'A', 'D', 'D', 'C', '8', 'r', 'p', 0,
  /* 3930 */ 'B', 'I', 'C', '8', 'r', 'p', 0,
  /* 3937 */ 'D', 'A', 'D', 'D', '8', 'r', 'p', 0,
  /* 3945 */ 'A', 'N', 'D', '8', 'r', 'p', 0,
  /* 3952 */ 'C', 'M', 'P', '8', 'r', 'p', 0,
  /* 3959 */ 'X', 'O', 'R', '8', 'r', 'p', 0,
  /* 3966 */ 'B', 'I', 'S', '8', 'r', 'p', 0,
  /* 3973 */ 'B', 'I', 'T', '8', 'r', 'p', 0,
  /* 3980 */ 'M', 'O', 'V', '8', 'r', 'p', 0,
  /* 3987 */ 'R', 'R', 'A', '1', '6', 'r', 0,
  /* 3994 */ 'S', 'W', 'P', 'B', '1', '6', 'r', 0,
  /* 4002 */ 'R', 'R', 'C', '1', '6', 'r', 0,
  /* 4009 */ 'P', 'U', 'S', 'H', '1', '6', 'r', 0,
  /* 4017 */ 'P', 'O', 'P', '1', '6', 'r', 0,
  /* 4024 */ 'S', 'E', 'X', 'T', '1', '6', 'r', 0,
  /* 4032 */ 'Z', 'E', 'X', 'T', '1', '6', 'r', 0,
  /* 4040 */ 'R', 'R', 'A', '8', 'r', 0,
  /* 4046 */ 'R', 'R', 'C', '8', 'r', 0,
  /* 4052 */ 'P', 'U', 'S', 'H', '8', 'r', 0,
  /* 4059 */ 'B', 'r', 0,
  /* 4062 */ 'C', 'A', 'L', 'L', 'r', 0,
  /* 4068 */ 'S', 'U', 'B', '1', '6', 'm', 'r', 0,
  /* 4076 */ 'S', 'U', 'B', 'C', '1', '6', 'm', 'r', 0,
  /* 4085 */ 'A', 'D', 'D', 'C', '1', '6', 'm', 'r', 0,
  /* 4094 */ 'B', 'I', 'C', '1', '6', 'm', 'r', 0,
  /* 4102 */ 'D', 'A', 'D', 'D', '1', '6', 'm', 'r', 0,
  /* 4111 */ 'A', 'N', 'D', '1', '6', 'm', 'r', 0,
  /* 4119 */ 'C', 'M', 'P', '1', '6', 'm', 'r', 0,
  /* 4127 */ 'X', 'O', 'R', '1', '6', 'm', 'r', 0,
  /* 4135 */ 'B', 'I', 'S', '1', '6', 'm', 'r', 0,
  /* 4143 */ 'B', 'I', 'T', '1', '6', 'm', 'r', 0,
  /* 4151 */ 'M', 'O', 'V', '1', '6', 'm', 'r', 0,
  /* 4159 */ 'S', 'U', 'B', '8', 'm', 'r', 0,
  /* 4166 */ 'S', 'U', 'B', 'C', '8', 'm', 'r', 0,
  /* 4174 */ 'A', 'D', 'D', 'C', '8', 'm', 'r', 0,
  /* 4182 */ 'B', 'I', 'C', '8', 'm', 'r', 0,
  /* 4189 */ 'D', 'A', 'D', 'D', '8', 'm', 'r', 0,
  /* 4197 */ 'A', 'N', 'D', '8', 'm', 'r', 0,
  /* 4204 */ 'C', 'M', 'P', '8', 'm', 'r', 0,
  /* 4211 */ 'X', 'O', 'R', '8', 'm', 'r', 0,
  /* 4218 */ 'B', 'I', 'S', '8', 'm', 'r', 0,
  /* 4225 */ 'B', 'I', 'T', '8', 'm', 'r', 0,
  /* 4232 */ 'M', 'O', 'V', '8', 'm', 'r', 0,
  /* 4239 */ 'S', 'U', 'B', '1', '6', 'r', 'r', 0,
  /* 4247 */ 'S', 'U', 'B', 'C', '1', '6', 'r', 'r', 0,
  /* 4256 */ 'A', 'D', 'D', 'C', '1', '6', 'r', 'r', 0,
  /* 4265 */ 'B', 'I', 'C', '1', '6', 'r', 'r', 0,
  /* 4273 */ 'D', 'A', 'D', 'D', '1', '6', 'r', 'r', 0,
  /* 4282 */ 'A', 'N', 'D', '1', '6', 'r', 'r', 0,
  /* 4290 */ 'C', 'M', 'P', '1', '6', 'r', 'r', 0,
  /* 4298 */ 'X', 'O', 'R', '1', '6', 'r', 'r', 0,
  /* 4306 */ 'B', 'I', 'S', '1', '6', 'r', 'r', 0,
  /* 4314 */ 'B', 'I', 'T', '1', '6', 'r', 'r', 0,
  /* 4322 */ 'M', 'O', 'V', '1', '6', 'r', 'r', 0,
  /* 4330 */ 'S', 'U', 'B', '8', 'r', 'r', 0,
  /* 4337 */ 'S', 'U', 'B', 'C', '8', 'r', 'r', 0,
  /* 4345 */ 'A', 'D', 'D', 'C', '8', 'r', 'r', 0,
  /* 4353 */ 'B', 'I', 'C', '8', 'r', 'r', 0,
  /* 4360 */ 'D', 'A', 'D', 'D', '8', 'r', 'r', 0,
  /* 4368 */ 'A', 'N', 'D', '8', 'r', 'r', 0,
  /* 4375 */ 'C', 'M', 'P', '8', 'r', 'r', 0,
  /* 4382 */ 'X', 'O', 'R', '8', 'r', 'r', 0,
  /* 4389 */ 'B', 'I', 'S', '8', 'r', 'r', 0,
  /* 4396 */ 'B', 'I', 'T', '8', 'r', 'r', 0,
  /* 4403 */ 'M', 'O', 'V', '8', 'r', 'r', 0,
};

extern const unsigned MSP430InstrNameIndices[] = {
    858U, 1094U, 1412U, 1212U, 915U, 896U, 924U, 1055U, 
    735U, 750U, 715U, 777U, 1634U, 636U, 905U, 507U, 
    2092U, 579U, 1913U, 426U, 1293U, 1043U, 1860U, 466U, 
    1849U, 586U, 1373U, 1360U, 1438U, 1740U, 1754U, 975U, 
    1022U, 995U, 941U, 365U, 140U, 1067U, 2010U, 2017U, 
    1080U, 1087U, 404U, 1540U, 1518U, 713U, 856U, 2078U, 
    646U, 1708U, 1578U, 1928U, 1595U, 1486U, 214U, 1617U, 
    1871U, 1560U, 1945U, 188U, 448U, 334U, 278U, 308U, 
    319U, 259U, 289U, 615U, 599U, 1651U, 791U, 808U, 
    371U, 146U, 410U, 387U, 1545U, 1524U, 2062U, 1189U, 
    2045U, 1172U, 348U, 123U, 499U, 439U, 1727U, 166U, 
    1681U, 1987U, 206U, 1838U, 1826U, 1903U, 832U, 1980U, 
    764U, 1996U, 961U, 1470U, 1463U, 1341U, 1334U, 1718U, 
    1269U, 528U, 1253U, 491U, 1261U, 520U, 1245U, 483U, 
    1285U, 1277U, 848U, 840U, 341U, 116U, 1060U, 110U, 
    252U, 2003U, 1073U, 2024U, 1400U, 17U, 825U, 9U, 
    0U, 728U, 1972U, 178U, 862U, 876U, 1316U, 1325U, 
    1571U, 1146U, 661U, 1126U, 1136U, 536U, 551U, 1104U, 
    1115U, 1310U, 885U, 1158U, 2031U, 1165U, 2038U, 1407U, 
    1778U, 1806U, 1785U, 1501U, 2104U, 695U, 2097U, 677U, 
    1352U, 1302U, 623U, 967U, 1610U, 1205U, 1937U, 1477U, 
    1882U, 1890U, 1955U, 1425U, 566U, 235U, 2154U, 2522U, 
    2915U, 3305U, 3695U, 4103U, 2325U, 2693U, 3086U, 3476U, 
    3851U, 4274U, 2241U, 2609U, 3002U, 3392U, 3774U, 4190U, 
    2412U, 2780U, 3173U, 3563U, 3938U, 4361U, 2136U, 2504U, 
    2897U, 3287U, 3677U, 4085U, 2307U, 2675U, 3068U, 3458U, 
    3833U, 4256U, 2225U, 2593U, 2986U, 3376U, 3758U, 4174U, 
    2396U, 2764U, 3157U, 3547U, 3922U, 4345U, 2461U, 1228U, 
    1385U, 2162U, 2530U, 2923U, 3313U, 3703U, 4111U, 2333U, 
    2701U, 3094U, 3484U, 3859U, 4282U, 2248U, 2616U, 3009U, 
    3399U, 3781U, 4197U, 2419U, 2787U, 3180U, 3570U, 3945U, 
    4368U, 2145U, 2513U, 2906U, 3296U, 3686U, 4094U, 2316U, 
    2684U, 3077U, 3467U, 3842U, 4265U, 2233U, 2601U, 2994U, 
    3384U, 3766U, 4182U, 2404U, 2772U, 3165U, 3555U, 3930U, 
    4353U, 2186U, 2554U, 2947U, 3337U, 3727U, 4135U, 2357U, 
    2725U, 3118U, 3508U, 3883U, 4306U, 2269U, 2637U, 3030U, 
    3420U, 3802U, 4218U, 2440U, 2808U, 3201U, 3591U, 3966U, 
    4389U, 2194U, 2562U, 2955U, 3345U, 3735U, 4143U, 2365U, 
    2733U, 3126U, 3516U, 3891U, 4314U, 2276U, 2644U, 3037U, 
    3427U, 3809U, 4225U, 2447U, 2815U, 3208U, 3598U, 3973U, 
    4396U, 2478U, 2871U, 4059U, 2481U, 2874U, 3264U, 3654U, 
    4062U, 2170U, 2538U, 2931U, 3321U, 3711U, 4119U, 2341U, 
    2709U, 3102U, 3492U, 3867U, 4290U, 2255U, 2623U, 3016U, 
    3406U, 3788U, 4204U, 2426U, 2794U, 3187U, 3577U, 3952U, 
    4375U, 2153U, 2521U, 2914U, 3304U, 3694U, 4102U, 2324U, 
    2692U, 3085U, 3475U, 3850U, 4273U, 2240U, 2608U, 3001U, 
    3391U, 3773U, 4189U, 2411U, 2779U, 3172U, 3562U, 3937U, 
    4360U, 162U, 1348U, 2202U, 2570U, 2963U, 3353U, 4151U, 
    2373U, 2741U, 3134U, 3524U, 3899U, 4322U, 2283U, 2651U, 
    3044U, 3434U, 4232U, 2454U, 2822U, 3215U, 3605U, 3980U, 
    4403U, 80U, 91U, 4017U, 2111U, 2470U, 4009U, 4052U, 
    1750U, 871U, 2829U, 3222U, 3612U, 3987U, 2859U, 3252U, 
    3642U, 4040U, 2844U, 3237U, 3627U, 4002U, 2865U, 3258U, 
    3648U, 4046U, 31U, 64U, 2851U, 3244U, 3634U, 4024U, 
    2119U, 2487U, 2880U, 3270U, 3660U, 4068U, 2290U, 2658U, 
    3051U, 3441U, 3816U, 4239U, 2210U, 2578U, 2971U, 3361U, 
    3743U, 4159U, 2381U, 2749U, 3142U, 3532U, 3907U, 4330U, 
    2127U, 2495U, 2888U, 3278U, 3668U, 4076U, 2298U, 2666U, 
    3059U, 3449U, 3824U, 4247U, 2217U, 2585U, 2978U, 3368U, 
    3750U, 4166U, 2388U, 2756U, 3149U, 3539U, 3914U, 4337U, 
    2836U, 3229U, 3619U, 3994U, 50U, 102U, 38U, 70U, 
    25U, 59U, 44U, 75U, 2178U, 2546U, 2939U, 3329U, 
    3719U, 4127U, 2349U, 2717U, 3110U, 3500U, 3875U, 4298U, 
    2262U, 2630U, 3023U, 3413U, 3795U, 4211U, 2433U, 2801U, 
    3194U, 3584U, 3959U, 4382U, 4032U, 
};

static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 517);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct MSP430GenInstrInfo : public TargetInstrInfo {
  explicit MSP430GenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
  ~MSP430GenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const MCInstrDesc MSP430Insts[];
extern const unsigned MSP430InstrNameIndices[];
extern const char MSP430InstrNameData[];
MSP430GenInstrInfo::MSP430GenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(MSP430Insts, MSP430InstrNameIndices, MSP430InstrNameData, 517);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace MSP430 {
namespace OpName {
enum {
OPERAND_LAST
};
} // end namespace OpName
} // end namespace MSP430
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace MSP430 {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  return -1;
}
} // end namespace MSP430
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace MSP430 {
namespace OpTypes {
enum OperandType {
  cc = 0,
  cg16imm = 1,
  cg8imm = 2,
  f32imm = 3,
  f64imm = 4,
  i16imm = 5,
  i1imm = 6,
  i32imm = 7,
  i64imm = 8,
  i8imm = 9,
  indreg = 10,
  jmptarget = 11,
  memdst = 12,
  memsrc = 13,
  postreg = 14,
  ptype0 = 15,
  ptype1 = 16,
  ptype2 = 17,
  ptype3 = 18,
  ptype4 = 19,
  ptype5 = 20,
  type0 = 21,
  type1 = 22,
  type2 = 23,
  type3 = 24,
  type4 = 25,
  type5 = 26,
  untyped_imm_0 = 27,
  GR16 = 28,
  GR8 = 29,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace MSP430 {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  const int Offsets[] = {
    0,
    1,
    1,
    1,
    2,
    3,
    4,
    5,
    5,
    8,
    12,
    13,
    17,
    20,
    20,
    21,
    23,
    25,
    25,
    26,
    27,
    29,
    29,
    35,
    36,
    36,
    38,
    39,
    39,
    39,
    39,
    39,
    39,
    41,
    44,
    44,
    47,
    50,
    53,
    56,
    59,
    62,
    65,
    68,
    71,
    74,
    75,
    76,
    78,
    80,
    83,
    85,
    89,
    91,
    93,
    95,
    97,
    99,
    101,
    103,
    105,
    107,
    109,
    111,
    113,
    118,
    123,
    128,
    130,
    135,
    140,
    144,
    147,
    150,
    153,
    156,
    159,
    162,
    165,
    168,
    171,
    174,
    177,
    180,
    183,
    185,
    187,
    188,
    189,
    190,
    192,
    194,
    196,
    198,
    199,
    202,
    204,
    207,
    209,
    212,
    215,
    218,
    222,
    226,
    230,
    234,
    239,
    243,
    248,
    252,
    257,
    261,
    266,
    270,
    274,
    277,
    280,
    283,
    286,
    289,
    293,
    297,
    300,
    303,
    306,
    308,
    310,
    312,
    314,
    316,
    318,
    320,
    322,
    324,
    326,
    328,
    330,
    332,
    335,
    337,
    340,
    343,
    346,
    349,
    352,
    355,
    358,
    361,
    364,
    367,
    370,
    373,
    374,
    377,
    381,
    384,
    388,
    390,
    392,
    394,
    396,
    398,
    400,
    402,
    404,
    406,
    408,
    410,
    412,
    414,
    416,
    418,
    420,
    422,
    425,
    428,
    431,
    435,
    438,
    441,
    444,
    447,
    450,
    454,
    457,
    461,
    464,
    467,
    470,
    474,
    477,
    480,
    483,
    486,
    489,
    493,
    496,
    500,
    503,
    506,
    509,
    513,
    516,
    519,
    522,
    525,
    528,
    532,
    535,
    539,
    542,
    545,
    548,
    552,
    555,
    558,
    561,
    564,
    567,
    571,
    574,
    578,
    581,
    584,
    586,
    588,
    591,
    594,
    598,
    601,
    604,
    607,
    610,
    613,
    617,
    620,
    624,
    627,
    630,
    633,
    637,
    640,
    643,
    646,
    649,
    652,
    656,
    659,
    663,
    666,
    669,
    672,
    676,
    679,
    682,
    685,
    688,
    691,
    695,
    698,
    702,
    705,
    708,
    711,
    715,
    718,
    721,
    724,
    727,
    730,
    734,
    737,
    741,
    744,
    747,
    750,
    754,
    757,
    760,
    763,
    766,
    769,
    773,
    776,
    780,
    783,
    786,
    789,
    793,
    796,
    799,
    802,
    805,
    808,
    812,
    815,
    819,
    822,
    825,
    828,
    832,
    835,
    838,
    841,
    843,
    845,
    848,
    850,
    852,
    854,
    857,
    860,
    864,
    867,
    870,
    873,
    875,
    877,
    880,
    882,
    884,
    886,
    887,
    889,
    890,
    891,
    893,
    894,
    895,
    896,
    899,
    902,
    906,
    909,
    912,
    915,
    917,
    919,
    922,
    924,
    926,
    928,
    931,
    934,
    938,
    941,
    944,
    947,
    949,
    951,
    954,
    956,
    958,
    960,
    963,
    966,
    970,
    973,
    976,
    979,
    982,
    985,
    989,
    992,
    996,
    999,
    1002,
    1005,
    1009,
    1012,
    1015,
    1018,
    1021,
    1024,
    1028,
    1031,
    1035,
    1038,
    1040,
    1041,
    1044,
    1047,
    1051,
    1054,
    1057,
    1059,
    1061,
    1064,
    1066,
    1069,
    1071,
    1074,
    1077,
    1081,
    1084,
    1087,
    1089,
    1091,
    1094,
    1096,
    1099,
    1101,
    1104,
    1106,
    1107,
    1108,
    1109,
    1110,
    1111,
    1111,
    1111,
    1113,
    1114,
    1115,
    1117,
    1119,
    1120,
    1121,
    1123,
    1125,
    1126,
    1127,
    1129,
    1131,
    1132,
    1133,
    1135,
    1137,
    1139,
    1141,
    1142,
    1143,
    1145,
    1148,
    1151,
    1155,
    1158,
    1161,
    1164,
    1167,
    1170,
    1174,
    1177,
    1181,
    1184,
    1187,
    1190,
    1194,
    1197,
    1200,
    1203,
    1206,
    1209,
    1213,
    1216,
    1220,
    1223,
    1226,
    1229,
    1233,
    1236,
    1239,
    1242,
    1245,
    1248,
    1252,
    1255,
    1259,
    1262,
    1265,
    1268,
    1272,
    1275,
    1278,
    1281,
    1284,
    1287,
    1291,
    1294,
    1298,
    1301,
    1303,
    1304,
    1305,
    1307,
    1311,
    1315,
    1318,
    1321,
    1324,
    1327,
    1330,
    1333,
    1336,
    1339,
    1343,
    1346,
    1349,
    1352,
    1355,
    1358,
    1362,
    1365,
    1369,
    1372,
    1375,
    1378,
    1382,
    1385,
    1388,
    1391,
    1394,
    1397,
    1401,
    1404,
    1408,
    1411,
  };
  const int OpcodeOperandTypes[] = {
    -1, 
    /**/
    /**/
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    /**/
    -1, -1, OpTypes::i32imm, 
    -1, -1, -1, OpTypes::i32imm, 
    -1, 
    -1, -1, -1, OpTypes::i32imm, 
    -1, -1, OpTypes::i32imm, 
    /**/
    -1, 
    -1, -1, 
    -1, -1, 
    /**/
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i64imm, OpTypes::i32imm, 
    /**/
    -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, 
    -1, 
    /**/
    -1, OpTypes::i32imm, 
    -1, 
    /**/
    /**/
    /**/
    /**/
    /**/
    -1, OpTypes::i8imm, 
    OpTypes::i16imm, -1, OpTypes::i32imm, 
    /**/
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, 
    OpTypes::type0, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::type0, -1, 
    OpTypes::type0, 
    -1, 
    -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, -1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    -1, 
    OpTypes::ptype0, -1, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, 
    OpTypes::type0, OpTypes::type1, OpTypes::type2, 
    OpTypes::type0, OpTypes::type1, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, 
    OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::jmptarget, OpTypes::cc, 
    OpTypes::jmptarget, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR8, 
    OpTypes::GR16, 
    OpTypes::cg16imm, 
    OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR8, 
    /**/
    /**/
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, 
    OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::cg16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::GR16, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::cg8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::i8imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR16, 
    OpTypes::GR16, OpTypes::i16imm, OpTypes::GR8, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::cg8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::i8imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, OpTypes::i16imm, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR16, OpTypes::GR8, OpTypes::GR16, 
    OpTypes::GR8, OpTypes::GR8, OpTypes::GR8, 
    OpTypes::GR16, OpTypes::GR16, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace MSP430
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE