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| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
namespace llvm {
} // end namespace llvm
#endif // GET_SUBTARGETINFO_ENUM
#ifdef GET_SUBTARGETINFO_MC_DESC
#undef GET_SUBTARGETINFO_MC_DESC
namespace llvm {
#ifdef DBGFIELD
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
#endif
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define DBGFIELD(x) x,
#else
#define DBGFIELD(x)
#endif
// ===============================================================
// Data tables for the new per-operand machine model.
// {ProcResourceIdx, Cycles}
extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[] = {
{ 0, 0}, // Invalid
}; // XCoreWriteProcResTable
// {Cycles, WriteResourceID}
extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[] = {
{ 0, 0}, // Invalid
}; // XCoreWriteLatencyTable
// {UseIdx, WriteResourceID, Cycles}
extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[] = {
{0, 0, 0}, // Invalid
}; // XCoreReadAdvanceTable
#undef DBGFIELD
static const llvm::MCSchedModel NoSchedModel = {
MCSchedModel::DefaultIssueWidth,
MCSchedModel::DefaultMicroOpBufferSize,
MCSchedModel::DefaultLoopMicroOpBufferSize,
MCSchedModel::DefaultLoadLatency,
MCSchedModel::DefaultHighLatency,
MCSchedModel::DefaultMispredictPenalty,
false, // PostRAScheduler
false, // CompleteModel
0, // Processor ID
nullptr, nullptr, 0, 0, // No instruction-level machine model.
nullptr, // No Itinerary
nullptr // No extra processor descriptor
};
// Sorted (by key) array of values for CPU subtype.
extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[] = {
{ "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
{ "xs1b-generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
};
namespace XCore_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
const MCInst *MI, unsigned CPUID) {
// Don't know how to resolve this scheduling class.
return 0;
}
} // end namespace XCore_MC
struct XCoreGenMCSubtargetInfo : public MCSubtargetInfo {
XCoreGenMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP) :
MCSubtargetInfo(TT, CPU, FS, PF, PD,
WPR, WL, RA, IS, OC, FP) { }
unsigned resolveVariantSchedClass(unsigned SchedClass,
const MCInst *MI, unsigned CPUID) const override {
return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
}
};
static inline MCSubtargetInfo *createXCoreMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
return new XCoreGenMCSubtargetInfo(TT, CPU, FS, None, XCoreSubTypeKV,
XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
nullptr, nullptr, nullptr);
}
} // end namespace llvm
#endif // GET_SUBTARGETINFO_MC_DESC
#ifdef GET_SUBTARGETINFO_TARGET_DESC
#undef GET_SUBTARGETINFO_TARGET_DESC
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options.
void llvm::XCoreSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
}
#endif // GET_SUBTARGETINFO_TARGET_DESC
#ifdef GET_SUBTARGETINFO_HEADER
#undef GET_SUBTARGETINFO_HEADER
namespace llvm {
class DFAPacketizer;
namespace XCore_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
} // end namespace XCore_MC
struct XCoreGenSubtargetInfo : public TargetSubtargetInfo {
explicit XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
public:
unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
};
} // end namespace llvm
#endif // GET_SUBTARGETINFO_HEADER
#ifdef GET_SUBTARGETINFO_CTOR
#undef GET_SUBTARGETINFO_CTOR
#include "llvm/CodeGen/TargetSchedule.h"
namespace llvm {
extern const llvm::SubtargetFeatureKV XCoreFeatureKV[];
extern const llvm::SubtargetSubTypeKV XCoreSubTypeKV[];
extern const llvm::MCWriteProcResEntry XCoreWriteProcResTable[];
extern const llvm::MCWriteLatencyEntry XCoreWriteLatencyTable[];
extern const llvm::MCReadAdvanceEntry XCoreReadAdvanceTable[];
XCoreGenSubtargetInfo::XCoreGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
: TargetSubtargetInfo(TT, CPU, FS, None, makeArrayRef(XCoreSubTypeKV, 2),
XCoreWriteProcResTable, XCoreWriteLatencyTable, XCoreReadAdvanceTable,
nullptr, nullptr, nullptr) {}
unsigned XCoreGenSubtargetInfo
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
report_fatal_error("Expected a variant SchedClass");
} // XCoreGenSubtargetInfo::resolveSchedClass
unsigned XCoreGenSubtargetInfo
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
return XCore_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
} // XCoreGenSubtargetInfo::resolveVariantSchedClass
} // end namespace llvm
#endif // GET_SUBTARGETINFO_CTOR
#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
|