reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1506   case ISD::ADDCARRY:           return visitADDCARRY(N);
 2381   if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
 2482   if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
 2484     return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
 2488   if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
 2490       return DAG.getNode(ISD::ADDCARRY, DL,
 2641   if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
 2645       return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
 2650   if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
 2652       return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
 2687     return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
 2752   if (Carry0.getOpcode() == ISD::ADDCARRY &&
 2767     SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
 2769     return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
 2823     return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
 3147   if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
 3153       return DAG.getNode(ISD::ADDCARRY, DL,
10790   if ((N0.getOpcode() == ISD::ADDE || N0.getOpcode() == ISD::ADDCARRY) &&
10793       ((!LegalOperations && N0.getOpcode() == ISD::ADDCARRY) ||

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

 3343   case ISD::ADDCARRY:
 3349     bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

  148   case ISD::ADDCARRY:
 1200   case ISD::ADDCARRY:
 1772   case ISD::ADDCARRY:
 2138       N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
 2145       Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
 2310       CarryOp = ISD::ADDCARRY;

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 3054   case ISD::ADDCARRY:
 3074     else if (Opcode == ISD::ADDCARRY)

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  287   case ISD::ADDCARRY:                   return "addcarry";

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 5734     Next = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(VT, BoolType), Next,
 5748     Hi = DAG.getNode(ISD::ADDCARRY, dl, DAG.getVTList(HiLoVT, BoolType), Hi,
 7110   unsigned OpcCarry = IsAdd ? ISD::ADDCARRY : ISD::SUBCARRY;

lib/CodeGen/TargetLoweringBase.cpp

  667     setOperationAction(ISD::ADDCARRY, VT, Expand);

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  749   case ISD::ADDCARRY:
 1048   unsigned Opc = N->getOpcode() == ISD::ADDCARRY ? AMDGPU::V_ADDC_U32_e64

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 1706     SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,
 1708     SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,
 1721     SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,
 1723     SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,
 1725     SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,

lib/Target/AMDGPU/SIISelLowering.cpp

  235   setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
  701   setTargetDAGCombine(ISD::ADDCARRY);
 9529       Opc == ISD::ANY_EXTEND || Opc == ISD::ADDCARRY)
 9543     Opc = (Opc == ISD::SIGN_EXTEND) ? ISD::SUBCARRY : ISD::ADDCARRY;
 9546   case ISD::ADDCARRY: {
 9551     return DAG.getNode(ISD::ADDCARRY, SDLoc(N), RHS->getVTList(), Args);
 9597   if ((LHSOpc == ISD::ADD && Opc == ISD::ADDCARRY) ||
 9944   case ISD::ADDCARRY:

lib/Target/ARM/ARMISelLowering.cpp

 1022   setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
 8691   if (Op.getOpcode() == ISD::ADDCARRY) {
 9209   case ISD::ADDCARRY:
14337         Res = DAG.getNode(ISD::ADDCARRY, dl, VTs, Sub, Neg, Carry);
16181   if (!isOperationLegalOrCustom(ISD::ADDCARRY, HalfT) ||
16197   Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi,

lib/Target/Hexagon/HexagonISelLowering.cpp

 1346     setOperationAction(ISD::ADDCARRY, VT, Expand);
 1349   setOperationAction(ISD::ADDCARRY, MVT::i64, Custom);
 2783   if (Opc == ISD::ADDCARRY)
 2856     case ISD::ADDCARRY:

lib/Target/SystemZ/SystemZISelLowering.cpp

  175       setOperationAction(ISD::ADDCARRY, VT, Custom);
 3481   while (Carry.getOpcode() == ISD::ADDCARRY)
 3513   case ISD::ADDCARRY:
 4971   case ISD::ADDCARRY:

lib/Target/X86/X86ISelDAGToDAG.cpp

  597     case ISD::ADDCARRY:

lib/Target/X86/X86ISelLowering.cpp

 1795     setOperationAction(ISD::ADDCARRY, VT, Custom);
27268   unsigned Opc = Op.getOpcode() == ISD::ADDCARRY ? X86ISD::ADC : X86ISD::SBB;
27762   case ISD::ADDCARRY:
27914     Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi,