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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc92031 /*209754*/ /*SwitchOpcode*/ 107|128,2/*363*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->210121
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc35325 /* 74824*/ /*SwitchOpcode*/ 5|128,3/*389*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->75217
gen/lib/Target/ARM/ARMGenDAGISel.inc32206 /* 70871*/ /*SwitchOpcode*/ 25|128,5/*665*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->71540
gen/lib/Target/AVR/AVRGenDAGISel.inc 1110 /* 1921*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::ATOMIC_LOAD),// ->1955
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc63037 /*120734*/ /*SwitchOpcode*/ 68|128,6/*836*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->121574
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 260 /* 394*/ /*SwitchOpcode*/ 20, TARGET_VAL(ISD::ATOMIC_LOAD),// ->417
gen/lib/Target/Mips/MipsGenDAGISel.inc 6578 /* 12780*/ /*SwitchOpcode*/ 55|128,1/*183*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->12967
gen/lib/Target/PowerPC/PPCGenDAGISel.inc21944 /* 54579*/ /*SwitchOpcode*/ 3|128,1/*131*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->54714
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 4613 /* 8529*/ /*SwitchOpcode*/ 64|128,9/*1216*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->9749
gen/lib/Target/Sparc/SparcGenDAGISel.inc 1302 /* 2342*/ /*SwitchOpcode*/ 8|128,1/*136*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->2482
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 1275 /* 2193*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1305 /* 2246*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1335 /* 2298*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1365 /* 2351*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1395 /* 2403*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1424 /* 2459*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1823 /* 3224*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1851 /* 3274*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1879 /* 3323*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
1907 /* 3373*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3065 /* 5446*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3092 /* 5499*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3117 /* 5547*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3144 /* 5600*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3643 /* 6548*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3665 /* 6589*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3725 /* 6698*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
3750 /* 6748*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
4173 /* 7583*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
4193 /* 7621*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
5809 /* 10626*/ /*SwitchOpcode*/ 42|128,1/*170*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->10800
7238 /* 13430*/ /*SwitchOpcode*/ 64|128,2/*320*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->13754
12813 /* 24667*/ /*SwitchOpcode*/ 63|128,4/*575*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->25246
gen/lib/Target/X86/X86GenDAGISel.inc 8605 /* 18525*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
8847 /* 19084*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
8906 /* 19216*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
8962 /* 19337*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
9093 /* 19618*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
9275 /* 20041*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
9333 /* 20172*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
9463 /* 20447*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
9521 /* 20578*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
9651 /* 20853*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
53916 /*114253*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::ATOMIC_LOAD),// ->114337
56214 /*119066*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
61838 /*130583*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
61908 /*130733*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD),
include/llvm/CodeGen/SelectionDAGNodes.h 1423 N->getOpcode() == ISD::ATOMIC_LOAD ||
1440 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||
1480 N->getOpcode() == ISD::ATOMIC_LOAD ||
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2729 case ISD::ATOMIC_LOAD: {
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 163 case ISD::ATOMIC_LOAD:
1714 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 603 case ISD::ATOMIC_LOAD:
6545 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 4702 SDValue L = DAG.getAtomic(ISD::ATOMIC_LOAD, dl, MemVT, MemVT, InChain,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 99 case ISD::ATOMIC_LOAD: return "AtomicLoad";
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 700 Use->getOpcode() != ISD::ATOMIC_LOAD &&
lib/Target/AMDGPU/R600ISelLowering.cpp 266 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 732 setTargetDAGCombine(ISD::ATOMIC_LOAD);
9972 case ISD::ATOMIC_LOAD:
lib/Target/ARM/ARMISelLowering.cpp 1242 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
9226 case ISD::ATOMIC_LOAD:
lib/Target/Mips/MipsISelLowering.cpp 471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 85 case ISD::ATOMIC_LOAD:
lib/Target/PowerPC/PPCISelLowering.cpp 1088 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1593 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1599 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
3058 case ISD::ATOMIC_LOAD:
lib/Target/SystemZ/SystemZISelLowering.cpp 180 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
235 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
4984 case ISD::ATOMIC_LOAD:
5071 case ISD::ATOMIC_LOAD: {
lib/Target/X86/X86ISelLowering.cpp 477 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
28361 case ISD::ATOMIC_LOAD: {
45125 if (!Load.hasOneUse() || Load.getOpcode() != ISD::ATOMIC_LOAD)
lib/Target/XCore/XCoreISelLowering.cpp 154 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
221 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
939 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");