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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc98448 /*221859*/ /*SwitchOpcode*/ 26|128,4/*538*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->222401
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc48314 /*104005*/ /*SwitchOpcode*/ 25|128,3/*409*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->104418
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 6879 /* 27003*/ /*SwitchOpcode*/ 125|128,1/*253*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->27260
gen/lib/Target/AVR/AVRGenDAGISel.inc 1174 /* 2029*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->2066
gen/lib/Target/Mips/MipsGenDAGISel.inc23768 /* 44604*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->44674
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc68617 /*145095*/ /*SwitchOpcode*/ 105|128,1/*233*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->145332
gen/lib/Target/PowerPC/PPCGenDAGISel.inc22131 /* 54934*/ /*SwitchOpcode*/ 79, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->55016
gen/lib/Target/RISCV/RISCVGenDAGISel.inc11510 /* 21293*/ /*SwitchOpcode*/ 37|128,6/*805*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->22102
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc20665 /* 38805*/ /*SwitchOpcode*/ 44, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->38852
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 199 /* 253*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
233 /* 313*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
267 /* 372*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
301 /* 432*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
945 /* 1568*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
978 /* 1631*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
1515 /* 2633*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
1546 /* 2693*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
2051 /* 3628*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
2080 /* 3680*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
2109 /* 3731*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
2138 /* 3783*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
2805 /* 4971*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
2831 /* 5019*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
3227 /* 5761*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
3255 /* 5816*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
3827 /* 6900*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
3853 /* 6952*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
4255 /* 7737*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
4276 /* 7777*/ OPC_CheckOpcode, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),
5234 /* 9526*/ /*SwitchOpcode*/ 88|128,1/*216*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->9746
6313 /* 11605*/ /*SwitchOpcode*/ 105|128,2/*361*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->11970
13368 /* 25851*/ /*SwitchOpcode*/ 89|128,4/*601*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->26456
include/llvm/CodeGen/SelectionDAGNodes.h 1411 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3781 case ISD::ATOMIC_LOAD_SUB:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 167 case ISD::ATOMIC_LOAD_SUB:
1717 case ISD::ATOMIC_LOAD_SUB:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 593 case ISD::ATOMIC_LOAD_SUB:
6518 Opcode == ISD::ATOMIC_LOAD_SUB ||
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 4594 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 88 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub";
lib/CodeGen/TargetLoweringBase.cpp 461 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
lib/Target/AArch64/AArch64ISelLowering.cpp 508 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
3083 case ISD::ATOMIC_LOAD_SUB:
lib/Target/AMDGPU/SIISelLowering.cpp 738 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
9978 case ISD::ATOMIC_LOAD_SUB:
lib/Target/ARM/ARMISelLowering.cpp 1230 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
lib/Target/Mips/Mips16ISelLowering.cpp 134 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 185 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
223 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
4988 case ISD::ATOMIC_LOAD_SUB:
lib/Target/X86/X86ISelLowering.cpp 468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
27110 case ISD::ATOMIC_LOAD_SUB:
27151 if (Opc == ISD::ATOMIC_LOAD_SUB) {
27668 case ISD::ATOMIC_LOAD_SUB:
28423 case ISD::ATOMIC_LOAD_SUB:
37280 if (Opc != ISD::ATOMIC_LOAD_ADD && Opc != ISD::ATOMIC_LOAD_SUB)
37289 if (Opc == ISD::ATOMIC_LOAD_SUB)
37305 ISD::ATOMIC_LOAD_SUB, SDLoc(CmpLHS), CmpLHS.getValueType(),