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reference to multiple definitions → definitions
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References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc63623 /*138896*/ OPC_SwitchOpcode /*2 cases */, 117|128,43/*5621*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->144522
63630 /*138910*/ OPC_SwitchOpcode /*2 cases */, 106|128,3/*490*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->139405
63908 /*139589*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
63974 /*139748*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
64033 /*139895*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
64185 /*140241*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
64251 /*140400*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
64855 /*141835*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
65014 /*142195*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
65083 /*142360*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
65145 /*142513*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
65304 /*142873*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
65373 /*143038*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
66008 /*144535*/ OPC_SwitchOpcode /*2 cases */, 35|128,1/*163*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->144703
66146 /*144887*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
66211 /*145043*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
66276 /*145199*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
66342 /*145358*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
66401 /*145505*/ OPC_SwitchOpcode /*2 cases */, 10|128,5/*650*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->146160
67239 /*147472*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
67307 /*147634*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
67375 /*147796*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
67444 /*147961*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
67506 /*148114*/ OPC_SwitchOpcode /*2 cases */, 38|128,5/*678*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->148797
68456 /*150362*/ OPC_SwitchOpcode /*2 cases */, 117|128,43/*5621*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->155988
68463 /*150376*/ OPC_SwitchOpcode /*2 cases */, 106|128,3/*490*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->150871
68741 /*151055*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
68807 /*151214*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
68866 /*151361*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
69018 /*151707*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
69084 /*151866*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
69688 /*153301*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
69847 /*153661*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
69916 /*153826*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
69978 /*153979*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
70137 /*154339*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
70206 /*154504*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
70841 /*156001*/ OPC_SwitchOpcode /*2 cases */, 35|128,1/*163*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->156169
70979 /*156353*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
71044 /*156509*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
71109 /*156665*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
71175 /*156824*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
71234 /*156971*/ OPC_SwitchOpcode /*2 cases */, 10|128,5/*650*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->157626
72072 /*158938*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
72140 /*159100*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
72208 /*159262*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
72277 /*159427*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMINNUM_IEEE),
72339 /*159580*/ OPC_SwitchOpcode /*2 cases */, 38|128,5/*678*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->160263
75683 /*167983*/ /*SwitchOpcode*/ 76|128,1/*204*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->168191
gen/lib/Target/PowerPC/PPCGenDAGISel.inc37135 /* 94914*/ /*SwitchOpcode*/ 25|128,2/*281*/, TARGET_VAL(ISD::FMINNUM_IEEE),// ->95199
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3240 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2284 case ISD::FMINNUM_IEEE:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 8149 unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
8164 unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 407 case ISD::FMINNUM_IEEE:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 116 case ISD::FMINNUM_IEEE:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4065 case ISD::FMINNUM_IEEE:
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 186 case ISD::FMINNUM_IEEE: return "fminnum_ieee";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6123 ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
lib/CodeGen/TargetLoweringBase.cpp 637 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 523 case ISD::FMINNUM_IEEE:
3619 return ISD::FMINNUM_IEEE;
3620 case ISD::FMINNUM_IEEE:
3734 case ISD::FMINNUM_IEEE:
lib/Target/AMDGPU/SIISelLowering.cpp 408 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
410 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
588 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
590 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
613 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
708 setTargetDAGCombine(ISD::FMINNUM_IEEE);
4079 case ISD::FMINNUM_IEEE:
8780 case ISD::FMINNUM_IEEE:
9000 case ISD::FMINNUM_IEEE:
9170 (Opc == ISD::FMINNUM_IEEE && Op0.getOpcode() == ISD::FMAXNUM_IEEE) ||
9294 case ISD::FMINNUM_IEEE: {
9956 case ISD::FMINNUM_IEEE:
lib/Target/PowerPC/PPCISelLowering.cpp 554 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
555 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
lib/Target/X86/X86ISelLowering.cpp36234 case ISD::FMINNUM_IEEE: