|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc50602 /*108880*/ OPC_CheckChild2CondCode, ISD::SETLT,
50630 /*108956*/ OPC_CheckChild2CondCode, ISD::SETLT,
51104 /*110249*/ OPC_CheckChild2CondCode, ISD::SETLT,
51132 /*110325*/ OPC_CheckChild2CondCode, ISD::SETLT,
51606 /*111618*/ OPC_CheckChild2CondCode, ISD::SETLT,
51634 /*111694*/ OPC_CheckChild2CondCode, ISD::SETLT,
52084 /*112855*/ OPC_CheckChild2CondCode, ISD::SETLT,
52344 /*113478*/ OPC_CheckChild2CondCode, ISD::SETLT,
52604 /*114101*/ OPC_CheckChild2CondCode, ISD::SETLT,
60333 /*132015*/ OPC_CheckChild2CondCode, ISD::SETLT,
60423 /*132183*/ OPC_CheckChild2CondCode, ISD::SETLT,
60686 /*132663*/ OPC_CheckChild2CondCode, ISD::SETLT,
60924 /*133106*/ OPC_CheckChild2CondCode, ISD::SETLT,
61381 /*134203*/ OPC_CheckChild2CondCode, ISD::SETLT,
61840 /*135304*/ OPC_CheckChild2CondCode, ISD::SETLT,
62140 /*136012*/ OPC_CheckChild2CondCode, ISD::SETLT,
gen/lib/Target/BPF/BPFGenDAGISel.inc 2084 return (N->getZExtValue() == ISD::SETLT);
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc29712 /* 57335*/ OPC_CheckChild2CondCode, ISD::SETLT,
29802 /* 57510*/ OPC_CheckChild2CondCode, ISD::SETLT,
29877 /* 57664*/ OPC_CheckChild2CondCode, ISD::SETLT,
29940 /* 57797*/ OPC_CheckChild2CondCode, ISD::SETLT,
29972 /* 57857*/ OPC_CheckChild2CondCode, ISD::SETLT,
30048 /* 58013*/ OPC_CheckChild2CondCode, ISD::SETLT,
30080 /* 58073*/ OPC_CheckChild2CondCode, ISD::SETLT,
30156 /* 58229*/ OPC_CheckChild2CondCode, ISD::SETLT,
30188 /* 58289*/ OPC_CheckChild2CondCode, ISD::SETLT,
30306 /* 58521*/ OPC_CheckChild2CondCode, ISD::SETLT,
30461 /* 58867*/ OPC_CheckChild2CondCode, ISD::SETLT,
30913 /* 59734*/ OPC_CheckChild2CondCode, ISD::SETLT,
51538 /* 97102*/ OPC_CheckChild2CondCode, ISD::SETLT,
51694 /* 97381*/ OPC_CheckChild2CondCode, ISD::SETLT,
gen/lib/Target/Mips/MipsGenDAGISel.inc 1748 /* 3121*/ OPC_CheckChild2CondCode, ISD::SETLT,
1850 /* 3283*/ OPC_CheckChild2CondCode, ISD::SETLT,
1919 /* 3394*/ OPC_CheckChild2CondCode, ISD::SETLT,
2242 /* 4004*/ OPC_CheckChild2CondCode, ISD::SETLT,
2573 /* 4610*/ OPC_CheckChild2CondCode, ISD::SETLT,
2661 /* 4753*/ OPC_CheckChild2CondCode, ISD::SETLT,
2704 /* 4826*/ OPC_CheckChild2CondCode, ISD::SETLT,
4004 /* 7521*/ OPC_CheckChild2CondCode, ISD::SETLT,
16554 /* 30731*/ OPC_CheckChild2CondCode, ISD::SETLT,
16570 /* 30761*/ OPC_CheckChild2CondCode, ISD::SETLT,
16630 /* 30895*/ OPC_CheckChild2CondCode, ISD::SETLT,
16647 /* 30926*/ OPC_CheckChild2CondCode, ISD::SETLT,
16679 /* 30986*/ OPC_CheckChild2CondCode, ISD::SETLT,
16851 /* 31373*/ OPC_CheckChild2CondCode, ISD::SETLT,
16983 /* 31671*/ OPC_CheckChild2CondCode, ISD::SETLT,
17022 /* 31754*/ OPC_CheckChild2CondCode, ISD::SETLT,
17196 /* 32111*/ OPC_CheckChild2CondCode, ISD::SETLT,
17280 /* 32267*/ OPC_CheckChild2CondCode, ISD::SETLT,
17449 /* 32624*/ OPC_CheckChild2CondCode, ISD::SETLT,
17533 /* 32780*/ OPC_CheckChild2CondCode, ISD::SETLT,
17656 /* 33055*/ OPC_CheckChild2CondCode, ISD::SETLT,
17693 /* 33126*/ OPC_CheckChild2CondCode, ISD::SETLT,
17736 /* 33209*/ OPC_CheckChild2CondCode, ISD::SETLT,
17773 /* 33280*/ OPC_CheckChild2CondCode, ISD::SETLT,
17816 /* 33363*/ OPC_CheckChild2CondCode, ISD::SETLT,
17853 /* 33434*/ OPC_CheckChild2CondCode, ISD::SETLT,
17896 /* 33517*/ OPC_CheckChild2CondCode, ISD::SETLT,
17933 /* 33588*/ OPC_CheckChild2CondCode, ISD::SETLT,
18036 /* 33779*/ OPC_CheckChild2CondCode, ISD::SETLT,
18139 /* 33970*/ OPC_CheckChild2CondCode, ISD::SETLT,
29326 /* 55471*/ OPC_CheckCondCode, ISD::SETLT,
29478 /* 55830*/ OPC_CheckChild2CondCode, ISD::SETLT,
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58920 /*125026*/ OPC_CheckChild2CondCode, ISD::SETLT,
58934 /*125053*/ OPC_CheckChild2CondCode, ISD::SETLT,
58948 /*125080*/ OPC_CheckChild2CondCode, ISD::SETLT,
58962 /*125107*/ OPC_CheckChild2CondCode, ISD::SETLT,
58976 /*125134*/ OPC_CheckChild2CondCode, ISD::SETLT,
58990 /*125161*/ OPC_CheckChild2CondCode, ISD::SETLT,
59004 /*125188*/ OPC_CheckChild2CondCode, ISD::SETLT,
59018 /*125215*/ OPC_CheckChild2CondCode, ISD::SETLT,
59032 /*125242*/ OPC_CheckChild2CondCode, ISD::SETLT,
59046 /*125269*/ OPC_CheckChild2CondCode, ISD::SETLT,
59060 /*125296*/ OPC_CheckChild2CondCode, ISD::SETLT,
59074 /*125323*/ OPC_CheckChild2CondCode, ISD::SETLT,
62744 /*132490*/ OPC_CheckChild2CondCode, ISD::SETLT,
62768 /*132538*/ OPC_CheckChild2CondCode, ISD::SETLT,
62792 /*132586*/ OPC_CheckChild2CondCode, ISD::SETLT,
62806 /*132613*/ OPC_CheckChild2CondCode, ISD::SETLT,
62820 /*132640*/ OPC_CheckChild2CondCode, ISD::SETLT,
62844 /*132688*/ OPC_CheckChild2CondCode, ISD::SETLT,
62868 /*132736*/ OPC_CheckChild2CondCode, ISD::SETLT,
62882 /*132763*/ OPC_CheckChild2CondCode, ISD::SETLT,
65316 /*137918*/ OPC_CheckChild2CondCode, ISD::SETLT,
65345 /*137982*/ OPC_CheckChild2CondCode, ISD::SETLT,
65374 /*138046*/ OPC_CheckChild2CondCode, ISD::SETLT,
65403 /*138110*/ OPC_CheckChild2CondCode, ISD::SETLT,
66141 /*139741*/ OPC_CheckChild2CondCode, ISD::SETLT,
66325 /*140144*/ OPC_CheckChild2CondCode, ISD::SETLT,
66509 /*140547*/ OPC_CheckChild2CondCode, ISD::SETLT,
67188 /*142033*/ OPC_CheckChild2CondCode, ISD::SETLT,
67866 /*143488*/ OPC_CheckChild2CondCode, ISD::SETLT,
68296 /*144421*/ OPC_CheckChild2CondCode, ISD::SETLT,
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 3897 /* 8379*/ OPC_CheckChild2CondCode, ISD::SETLT,
3934 /* 8469*/ OPC_CheckChild2CondCode, ISD::SETLT,
4128 /* 9006*/ OPC_CheckChild2CondCode, ISD::SETLT,
4196 /* 9192*/ OPC_CheckChild2CondCode, ISD::SETLT,
4770 /* 10758*/ OPC_CheckChild2CondCode, ISD::SETLT,
4794 /* 10811*/ OPC_CheckChild2CondCode, ISD::SETLT,
4990 /* 11323*/ OPC_CheckChild2CondCode, ISD::SETLT,
5037 /* 11447*/ OPC_CheckChild2CondCode, ISD::SETLT,
7552 /* 18145*/ OPC_CheckChild2CondCode, ISD::SETLT,
7589 /* 18235*/ OPC_CheckChild2CondCode, ISD::SETLT,
7783 /* 18772*/ OPC_CheckChild2CondCode, ISD::SETLT,
7851 /* 18958*/ OPC_CheckChild2CondCode, ISD::SETLT,
8425 /* 20524*/ OPC_CheckChild2CondCode, ISD::SETLT,
8449 /* 20577*/ OPC_CheckChild2CondCode, ISD::SETLT,
8645 /* 21089*/ OPC_CheckChild2CondCode, ISD::SETLT,
8692 /* 21213*/ OPC_CheckChild2CondCode, ISD::SETLT,
25141 /* 60537*/ OPC_CheckChild2CondCode, ISD::SETLT,
25385 /* 61178*/ OPC_CheckChild2CondCode, ISD::SETLT,
25532 /* 61575*/ OPC_CheckChild2CondCode, ISD::SETLT,
25779 /* 62221*/ OPC_CheckChild2CondCode, ISD::SETLT,
25909 /* 62580*/ OPC_CheckChild2CondCode, ISD::SETLT,
25984 /* 62723*/ OPC_CheckChild2CondCode, ISD::SETLT,
26054 /* 62891*/ OPC_CheckChild2CondCode, ISD::SETLT,
26340 /* 63707*/ OPC_CheckChild2CondCode, ISD::SETLT,
26410 /* 63875*/ OPC_CheckChild2CondCode, ISD::SETLT,
26696 /* 64691*/ OPC_CheckChild2CondCode, ISD::SETLT,
26922 /* 65279*/ OPC_CheckChild2CondCode, ISD::SETLT,
27132 /* 65808*/ OPC_CheckChild2CondCode, ISD::SETLT,
28705 /* 68910*/ OPC_CheckCondCode, ISD::SETLT,
28865 /* 69370*/ OPC_CheckCondCode, ISD::SETLT,
28965 /* 69600*/ OPC_CheckCondCode, ISD::SETLT,
29065 /* 69830*/ OPC_CheckCondCode, ISD::SETLT,
29175 /* 70080*/ OPC_CheckCondCode, ISD::SETLT,
29285 /* 70330*/ OPC_CheckCondCode, ISD::SETLT,
29395 /* 70580*/ OPC_CheckCondCode, ISD::SETLT,
29505 /* 70830*/ OPC_CheckCondCode, ISD::SETLT,
29615 /* 71080*/ OPC_CheckCondCode, ISD::SETLT,
29725 /* 71330*/ OPC_CheckCondCode, ISD::SETLT,
29825 /* 71560*/ OPC_CheckCondCode, ISD::SETLT,
29935 /* 71810*/ OPC_CheckCondCode, ISD::SETLT,
30035 /* 72040*/ OPC_CheckCondCode, ISD::SETLT,
30145 /* 72290*/ OPC_CheckCondCode, ISD::SETLT,
30255 /* 72540*/ OPC_CheckCondCode, ISD::SETLT,
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 6727 /* 12403*/ OPC_CheckChild2CondCode, ISD::SETLT,
6804 /* 12564*/ OPC_CheckChild2CondCode, ISD::SETLT,
7022 /* 13027*/ OPC_CheckChild2CondCode, ISD::SETLT,
7061 /* 13110*/ OPC_CheckChild2CondCode, ISD::SETLT,
7210 /* 13420*/ OPC_CheckChild2CondCode, ISD::SETLT,
7431 /* 13900*/ OPC_CheckChild2CondCode, ISD::SETLT,
7719 /* 14495*/ OPC_CheckChild2CondCode, ISD::SETLT,
7917 /* 14817*/ OPC_CheckChild2CondCode, ISD::SETLT,
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 7603 /* 14101*/ OPC_CheckChild2CondCode, ISD::SETLT,
7676 /* 14233*/ OPC_CheckChild2CondCode, ISD::SETLT,
7777 /* 14417*/ OPC_CheckChild2CondCode, ISD::SETLT,
7853 /* 14556*/ OPC_CheckChild2CondCode, ISD::SETLT,
7896 /* 14635*/ OPC_CheckChild2CondCode, ISD::SETLT,
7970 /* 14773*/ OPC_CheckChild2CondCode, ISD::SETLT,
8045 /* 14914*/ OPC_CheckChild2CondCode, ISD::SETLT,
8159 /* 15125*/ OPC_CheckChild2CondCode, ISD::SETLT,
8242 /* 15278*/ OPC_CheckChild2CondCode, ISD::SETLT,
gen/lib/Target/XCore/XCoreGenDAGISel.inc 1363 /* 2251*/ OPC_CheckChild2CondCode, ISD::SETLT,
1529 /* 2563*/ OPC_CheckChild2CondCode, ISD::SETLT,
1783 /* 3094*/ OPC_CheckChild2CondCode, ISD::SETLT,
include/llvm/CodeGen/ISDOpcodes.h 1054 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
lib/CodeGen/Analysis.cpp 227 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT;
246 case ICmpInst::ICMP_SLT: return ISD::SETLT;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 3750 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
4450 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4465 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
8142 case ISD::SETLT:
8205 if (CC == ISD::SETLT && isNullOrNullSplat(CondC) && isNullOrNullSplat(C2)) {
8707 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
12293 case ISD::SETLT:
19743 CC == ISD::SETULT || CC == ISD::SETLT)) {
19925 } else if (CC == ISD::SETLT) {
20450 SDValue IsDenorm = DAG.getSetCC(DL, CCVT, Fabs, NormC, ISD::SETLT);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1706 case ISD::SETLT:
2408 DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
3097 case ISD::SMIN: Pred = ISD::SETLT; break;
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 1613 Lo, Hi, ISD::SETLT);
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1283 case ISD::SETLT:
2086 return std::make_pair(ISD::SETLT, ISD::UMIN);
2900 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
3041 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3050 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3054 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3068 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3675 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
3686 case ISD::SETLT:
3756 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
4020 ISD::SETLT);
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 376 case ISD::SETLT:
2027 case ISD::SETLT: return getBoolConstant(C1.slt(C2), dl, VT, OpVT);
2053 case ISD::SETLT: if (R==APFloat::cmpUnordered)
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp10414 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 418 case ISD::SETLT: return "setlt";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 305 case ISD::SETLT:
1260 if (CC == ISD::SETLT && Op1.getValueType().isInteger() &&
3314 case ISD::SETLT:
3528 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
3540 if (Cond == ISD::SETLT || Cond == ISD::SETULT) {
3593 ISD::SETLT);
3898 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
5756 Next = DAG.getSelectCC(dl, LH, Zero, NextSub, Next, ISD::SETLT);
5760 Next = DAG.getSelectCC(dl, RH, Zero, NextSub, Next, ISD::SETLT);
5945 DAG.getConstant(0, dl, DstVT), Ret, ISD::SETLT);
5986 SDValue Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT);
6078 dl, SetCCVT, Src, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
6956 SDValue SumNeg = DAG.getSetCC(dl, BoolVT, SumDiff, Zero, ISD::SETLT);
6998 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
7081 ISD::SETLT);
7098 Result = DAG.getSelectCC(dl, Hi, HighMask, SatMin, Result, ISD::SETLT);
7162 SDValue ResultLowerThanLHS = DAG.getSetCC(dl, OType, Result, LHS, ISD::SETLT);
7164 DAG.getSetCC(dl, OType, RHS, Zero, IsAdd ? ISD::SETLT : ISD::SETGT);
lib/CodeGen/TargetLoweringBase.cpp 543 CCs[RTLIB::OLT_F32] = ISD::SETLT;
544 CCs[RTLIB::OLT_F64] = ISD::SETLT;
545 CCs[RTLIB::OLT_F128] = ISD::SETLT;
546 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
lib/Target/AArch64/AArch64ISelLowering.cpp 1440 case ISD::SETLT:
1501 case ISD::SETLT:
1981 case ISD::SETLT:
1987 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2008 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4766 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
9354 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 1292 case ISD::SETLT: {
1990 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1991 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
2113 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2230 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2652 SDValue V = DAG.getSelectCC(DL, E, One, D, N, ISD::SETLT);
lib/Target/AMDGPU/R600ISelLowering.cpp 124 setCondCodeAction(ISD::SETLT, MVT::f32, Expand);
136 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 9804 (CC == ISD::SETNE || CC == ISD::SETUGT || CC == ISD::SETLT)))
lib/Target/AMDGPU/SIInsertSkips.cpp 208 case ISD::SETLT:
lib/Target/ARC/ARCISelLowering.cpp 61 case ISD::SETLT:
lib/Target/ARM/ARMISelLowering.cpp 1804 case ISD::SETLT: return ARMCC::LT;
1833 case ISD::SETLT:
4190 case ISD::SETLT:
4193 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4207 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4620 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4626 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4691 return CC == ISD::SETLT || CC == ISD::SETLE;
6223 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
6270 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
14125 (CC == ISD::SETLT && Imm == 1) ||
lib/Target/AVR/AVRISelLowering.cpp 432 case ISD::SETLT:
474 CC = ISD::SETLT;
489 CC = ISD::SETLT;
492 case ISD::SETLT: {
lib/Target/BPF/BPFISelLowering.cpp 490 case ISD::SETLT:
693 SET_NEWCC(SETLT, JSLT);
704 CC == ISD::SETLT ||
lib/Target/Hexagon/HexagonISelLowering.cpp 1509 setCondCodeAction(ISD::SETLT, VT, Expand);
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 118 setCondCodeAction(ISD::SETLT, T, Expand);
lib/Target/Lanai/LanaiISelLowering.cpp 822 case ISD::SETLT:
lib/Target/MSP430/MSP430ISelLowering.cpp 198 { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT },
204 { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT },
1095 case ISD::SETLT:
lib/Target/Mips/MipsISelLowering.cpp 610 case ISD::SETLT:
lib/Target/Mips/MipsSEISelLowering.cpp 955 case ISD::SETLT:
1754 Op->getOperand(2), ISD::SETLT);
1760 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 576 case ISD::SETLT:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 2990 case ISD::SETLT: {
3169 case ISD::SETLT: {
3324 case ISD::SETLT: {
3484 case ISD::SETLT: {
3781 case ISD::SETLT:
3808 case ISD::SETLT:
3848 case ISD::SETLT: return PPC::PRED_LT;
3871 case ISD::SETLT: return 0; // Bit #0 = SETOLT
3907 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
3953 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
4038 case ISD::SETLT: {
4077 case ISD::SETLT: {
4279 InnerCC = (InnerCC == ISD::SETULT) ? ISD::SETLT : ISD::SETGT;
4294 if (InnerCC != ISD::SETLT && InnerCC != ISD::SETGT)
4310 case ISD::SETLT:
4312 (InnerCC == ISD::SETLT && InnerSwapped))
4330 if (InnerCC == ISD::SETNE || (InnerCC == ISD::SETLT && !InnerSwapped) ||
lib/Target/PowerPC/PPCISelLowering.cpp 3084 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
7254 case ISD::SETLT:
7282 case ISD::SETLT:
7318 case ISD::SETLT:
lib/Target/RISCV/RISCVISelLowering.cpp 357 case ISD::SETLT:
751 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
803 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
lib/Target/Sparc/SparcISelLowering.cpp 1369 case ISD::SETLT: return SPCC::ICC_L;
1389 case ISD::SETLT:
lib/Target/SystemZ/SystemZISelLowering.cpp 1947 CONV(LT);
2460 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
lib/Target/X86/X86ISelLowering.cpp 903 setCondCodeAction(ISD::SETLT, VT, Custom);
1177 setCondCodeAction(ISD::SETLT, VT, Custom);
1466 setCondCodeAction(ISD::SETLT, VT, Custom);
1691 setCondCodeAction(ISD::SETLT, VT, Custom);
4672 case ISD::SETLT: return X86::COND_L;
4695 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4703 if (SetCCOpcode == ISD::SETLT && RHSC->getAPIntValue() == 1) {
4750 case ISD::SETLT: return X86::COND_B;
18872 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
18981 Value, ThreshVal, ISD::SETLT);
18989 Value, ThreshVal, ISD::SETLT);
20340 SDValue Cmp = DAG.getSetCC(DL, MVT::i8, N0, Zero, ISD::SETLT);
20464 case ISD::SETLT:
20531 if (SetCCOpcode == ISD::SETLT) {
20721 case ISD::SETLT: CmpMode = 0x00; break;
20789 Cond = ISD::SETLT;
20849 bool Swap = Cond == ISD::SETLT || Cond == ISD::SETULT ||
23170 case ISD::SETLT: { // The condition is opposite to GT. Swap the operands.
25007 case ISD::SMIN: CC = ISD::CondCode::SETLT; break;
35482 cast<CondCodeSDNode>(N0.getOperand(2))->get() == ISD::SETLT) {
36875 case ISD::SETLT:
36973 case ISD::SETLT:
37079 case ISD::SETLT:
37081 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
37144 if (CC == ISD::SETLT && Other.getOpcode() == ISD::XOR &&
42867 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
lib/Target/X86/X86InstrInfo.cpp 2318 case ISD::SETLT: return 1;
lib/Target/X86/X86IntrinsicsInfo.h 1004 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT),
1021 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
1028 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT),
1075 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT),