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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenDAGISel.inc53355 /*119272*/ /*SwitchOpcode*/ 85, TARGET_VAL(ISD::USUBSAT),// ->119360
gen/lib/Target/ARM/ARMGenFastISel.inc 5188 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc78011 /*164120*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::USUBSAT),// ->164185
83129 /*174211*/ /*SwitchOpcode*/ 62, TARGET_VAL(ISD::USUBSAT),// ->174276
100676 /*209217*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::USUBSAT),// ->209259
108094 /*224073*/ /*SwitchOpcode*/ 38, TARGET_VAL(ISD::USUBSAT),// ->224114
118730 /*245228*/ /*SwitchOpcode*/ 66, TARGET_VAL(ISD::USUBSAT),// ->245297
120729 /*249188*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::USUBSAT),// ->249304
124231 /*255900*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::USUBSAT),// ->255922
126682 /*260492*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::USUBSAT),// ->260513
145392 /*297552*/ OPC_CheckOpcode, TARGET_VAL(ISD::USUBSAT),
147351 /*301150*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::USUBSAT),// ->301187
187103 /*378203*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::USUBSAT),// ->378240
187898 /*379670*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::USUBSAT),// ->379707
188636 /*381103*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::USUBSAT),// ->381125
188964 /*381687*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::USUBSAT),// ->381708
214434 /*435182*/ /*SwitchOpcode*/ 51|128,3/*435*/, TARGET_VAL(ISD::USUBSAT),// ->435621
gen/lib/Target/X86/X86GenFastISel.inc13534 case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1498 case ISD::USUBSAT: return visitSUBSAT(N);
2226 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2233 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1121 case ISD::USUBSAT: {
3334 case ISD::USUBSAT:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 154 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break;
662 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
680 case ISD::USUBSAT:
700 if (Opcode == ISD::USUBSAT) {
1789 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 451 case ISD::USUBSAT:
826 case ISD::USUBSAT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 128 case ISD::USUBSAT:
961 case ISD::USUBSAT:
2750 case ISD::USUBSAT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4715 case ISD::USUBSAT: return std::make_pair(C1.usub_sat(C2), true);
5114 case ISD::USUBSAT:
5383 case ISD::USUBSAT:
5408 case ISD::USUBSAT:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6310 setValue(&I, DAG.getNode(ISD::USUBSAT, sdl, Op1.getValueType(), Op1, Op2));
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 304 case ISD::USUBSAT: return "usubsat";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6893 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
6915 case ISD::USUBSAT:
6940 } else if (Opcode == ISD::USUBSAT) {
lib/CodeGen/TargetLoweringBase.cpp 652 setOperationAction(ISD::USUBSAT, VT, Expand);
lib/Target/ARM/ARMISelLowering.cpp 271 setOperationAction(ISD::USUBSAT, VT, Legal);
lib/Target/X86/X86ISelLowering.cpp 881 setOperationAction(ISD::USUBSAT, MVT::v16i8, Legal);
885 setOperationAction(ISD::USUBSAT, MVT::v8i16, Legal);
888 setOperationAction(ISD::USUBSAT, MVT::v4i32, Custom);
890 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
1212 setOperationAction(ISD::USUBSAT, MVT::v32i8, HasInt256 ? Legal : Custom);
1216 setOperationAction(ISD::USUBSAT, MVT::v16i16, HasInt256 ? Legal : Custom);
1338 setOperationAction(ISD::USUBSAT, VT, Custom);
1601 setOperationAction(ISD::USUBSAT, VT, Custom);
1685 setOperationAction(ISD::USUBSAT, VT, Legal);
20621 SDValue Result = DAG.getNode(ISD::USUBSAT, dl, VT, Op0, Op1);
24910 case ISD::USUBSAT:
24929 if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) {
27768 case ISD::USUBSAT:
37118 return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
37135 return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
37150 return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
44165 return DAG.getNode(ISD::USUBSAT, SDLoc(N), VT, SubusLHS, SubusRHS);
44197 SDValue Psubus = DAG.getNode(ISD::USUBSAT, SDLoc(N), ShrinkedType,
lib/Target/X86/X86TargetTransformInfo.cpp 1923 { ISD::USUBSAT, MVT::v32i16, 1 },
1924 { ISD::USUBSAT, MVT::v64i8, 1 },
1935 { ISD::USUBSAT, MVT::v16i32, 2 }, // pmaxud + psubd
1936 { ISD::USUBSAT, MVT::v2i64, 2 }, // pmaxuq + psubq
1937 { ISD::USUBSAT, MVT::v4i64, 2 }, // pmaxuq + psubq
1938 { ISD::USUBSAT, MVT::v8i64, 2 }, // pmaxuq + psubq
1985 { ISD::USUBSAT, MVT::v16i16, 1 },
1986 { ISD::USUBSAT, MVT::v32i8, 1 },
1987 { ISD::USUBSAT, MVT::v8i32, 2 }, // pmaxud + psubd
2022 { ISD::USUBSAT, MVT::v16i16, 4 }, // 2 x 128-bit Op + extract/insert
2023 { ISD::USUBSAT, MVT::v32i8, 4 }, // 2 x 128-bit Op + extract/insert
2024 { ISD::USUBSAT, MVT::v8i32, 6 }, // 2 x 128-bit Op + extract/insert
2045 { ISD::USUBSAT, MVT::v4i32, 2 }, // pmaxud + psubd
2097 { ISD::USUBSAT, MVT::v8i16, 1 },
2098 { ISD::USUBSAT, MVT::v16i8, 1 },
2177 ISD = ISD::USUBSAT;