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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/LiveInterval.h 176 return start <= I && I < end;
182 return (start <= S && S < end) && (start < E && E <= end);
182 return (start <= S && S < end) && (start < E && E <= end);
186 return std::tie(start, end) < std::tie(Other.start, Other.end);
186 return std::tie(start, end) < std::tie(Other.start, Other.end);
189 return start == Other.start && end == Other.end;
189 return start == Other.start && end == Other.end;
254 segments.push_back(Segment(S.start, S.end, valnos[S.valno->id]));
378 return segments.front().start;
394 return r != end() && r->start <= index;
429 return I != end() && I->start <= Idx ? I : end();
434 return I != end() && I->start <= Idx ? I : end();
520 removeSegment(S.start, S.end, RemoveDeadValNo);
546 if (I->start <= Idx.getBaseIndex()) {
564 if (!SlotIndex::isEarlierInstr(Idx, I->start)) {
579 if (Indexes->getNextNonNullIndex(S.start).getBaseIndex() <
636 auto NotLessStart = std::lower_bound(Idx, EndIdx, Seg->start);
887 return V < S.start;
891 return S.start < V;
lib/CodeGen/InterferenceCache.cpp 185 SlotIndex StartI = I->start;
238 if (I == LR->end() || I->start >= Stop)
241 bool Backup = I == LR->end() || I->start >= Stop;
lib/CodeGen/LiveDebugVariables.cpp 1040 if (LocMapI.value().locNo() == OldLocNo && LII->start < LocMapI.stop()) {
1054 if (LStart < LII->start)
1055 LocMapI.setStartUnchecked(LII->start);
1079 LocMapI.advanceTo(LII->start);
lib/CodeGen/LiveInterval.cpp 100 if (SlotIndex::isSameInstr(Def, S->start)) {
102 assert(S->valno->def == S->start && "Inconsistent existing value def");
109 Def = std::min(Def, S->start);
110 if (Def != S->start)
111 S->start = S->valno->def = Def;
114 assert(SlotIndex::isEarlierInstr(Def, S->start) && "Already live at def");
173 if (MergeTo != segments().end() && MergeTo->start <= I->end &&
195 S->start = NewStart;
201 } while (NewStart <= MergeTo->start);
211 MergeToSeg->start = NewStart;
220 SlotIndex Start = S.start, End = S.end;
228 if (B->start <= Start && B->end >= Start) {
245 if (I->start <= End) {
257 assert(I->start >= End &&
299 iterator findInsertPos(Segment S) { return llvm::upper_bound(*LR, S.start); }
338 if (I != LR->segmentSet->end() && !(S.start < *I))
412 assert((StartPos->start <= i->start || StartPos == other.begin()) &&
412 assert((StartPos->start <= i->start || StartPos == other.begin()) &&
415 if (i->start < j->start) {
415 if (i->start < j->start) {
416 i = std::upper_bound(i, ie, j->start);
418 } else if (j->start < i->start) {
418 } else if (j->start < i->start) {
420 if (StartPos != other.end() && StartPos->start <= i->start) {
420 if (StartPos != other.end() && StartPos->start <= i->start) {
422 j = std::upper_bound(j, je, i->start);
432 if (i->start > j->start) {
432 if (i->start > j->start) {
437 if (i->end > j->start)
456 const_iterator J = Other.find(I->start);
463 assert(J->end >= I->start);
465 if (J->start < I->end) {
467 SlotIndex Def = std::max(I->start, J->start);
467 SlotIndex Def = std::max(I->start, J->start);
482 while (J->end < I->start);
500 I = advanceTo(I, O.start);
501 if (I == end() || I->start > O.start)
501 if (I == end() || I->start > O.start)
509 if (I == end() || Last->end != I->start)
560 assert(segments.empty() || segments.back().end <= S.start);
593 if (I->start == Start) {
611 I->start = End;
674 if (OutIt->valno == nextValNo && OutIt->end == I->start) {
681 OutIt->start = I->start;
681 OutIt->start = I->start;
728 Updater.add(S.start, S.end, LHSValNo);
742 Updater.add(S.start, S.end, LHSValNo);
772 if (Prev->valno == V2 && Prev->end == S->start) {
790 if (I->start == S->end && I->valno == V2) {
963 Sum += S.start.distance(S.end);
992 return OS << '[' << S.start << ',' << S.end << ':' << S.valno->id << ')';
1062 assert(I->start.isValid());
1064 assert(I->start < I->end);
1069 assert(I->end <= std::next(I)->start);
1070 if (I->end == std::next(I)->start)
1161 assert(A.start <= B.start && "Unordered live segments.");
1161 assert(A.start <= B.start && "Unordered live segments.");
1162 if (A.end == B.start)
1164 if (A.end < B.start)
1181 if (!LastStart.isValid() || LastStart > Seg.start) {
1190 LastStart = Seg.start;
1194 if (ReadI != E && ReadI->end <= Seg.start) {
1200 ReadI = WriteI = LR->find(Seg.start);
1202 while (ReadI != E && ReadI->end <= Seg.start)
1206 assert(ReadI == E || ReadI->end > Seg.start);
1209 if (ReadI != E && ReadI->start <= Seg.start) {
1209 if (ReadI != E && ReadI->start <= Seg.start) {
1215 Seg.start = ReadI->start;
1215 Seg.start = ReadI->start;
1227 Seg.start = Spills.back().start;
1227 Seg.start = Spills.back().start;
1268 if (Src != B && Src[-1].start > SpillSrc[-1].start)
1268 if (Src != B && Src[-1].start > SpillSrc[-1].start)
lib/CodeGen/LiveIntervalUnion.cpp 37 SegmentIter SegPos = Segments.find(RegPos->start);
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
43 SegPos.advanceTo(RegPos->start);
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
64 SegmentIter SegPos = Segments.find(RegPos->start);
77 SegPos.advanceTo(RegPos->start);
136 LiveUnionI.find(LRI->start);
145 while (LRI->start < LiveUnionI.stop() && LRI->end > LiveUnionI.start()) {
171 if (LRI->start < LiveUnionI.stop())
175 LiveUnionI.advanceTo(LRI->start);
lib/CodeGen/LiveIntervals.cpp 741 if (I == RURange.end() || I->start >= RI->end)
769 if (I == SR.end() || I->start >= RI->end)
800 if (N != LI.end() && N->start == RI->end)
903 ArrayRef<SlotIndex>::iterator SlotI = llvm::lower_bound(Slots, LiveI->start);
912 assert(*SlotI >= LiveI->start);
932 while (*SlotI < LiveI->start)
1051 if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1056 if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1070 if (Next != E && !SlotIndex::isSameInstr(OldIdx, Next->start) &&
1071 SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1078 !SlotIndex::isEarlierInstr(NewIdxIn->start, NewIdx)) {
1083 OldIdxIn->end = Next->start;
1097 if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1105 assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1108 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1112 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1115 OldIdxOut->start = OldIdxVNI->def;
1132 OldIdxOut->start)) {
1147 INext->start = OldIdxOut->end;
1148 INext->valno->def = INext->start;
1173 if (SlotIndex::isEarlierInstr(Prev->start, NewIdxDef)) {
1180 *Prev = LiveRange::Segment(Prev->start, NewIdxDef, DefVNI);
1181 DefVNI->def = Prev->start;
1185 *Prev = LiveRange::Segment(NewIdxDef, AfterNewIdx->start, DefVNI);
1194 SlotIndex::isSameInstr(AfterNewIdx->start, NewIdxDef)) {
1224 if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1229 if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1240 = std::max(OldIdxIn->start.getDeadSlot(),
1246 if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1255 assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1258 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1262 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1264 if (SlotIndex::isSameInstr(NewIdxOut->start, NewIdx)) {
1272 OldIdxOut->start = NewIdxDef;
1284 SlotIndex::isEarlierInstr(NewIdxDef, OldIdxIn->start)) {
1301 NewDefEndPoint = std::min(OldIdxIn->start,
1302 std::next(NewIdxOut)->start);
1306 OldIdxOut->valno->def = OldIdxIn->start;
1307 *OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,
1318 if (SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1320 *NewSegment = LiveRange::Segment(Next->start, SplitPos,
1328 *NewSegment = LiveRange::Segment(SplitPos, Next->start, OldIdxVNI);
1333 OldIdxOut->start = NewIdxDef;
1339 && SlotIndex::isEarlierInstr(NewIdxOut->start, NewIdx)
1354 NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);
1493 if (LII != LR.end() && LII->start < endIdx)
1505 bool isStartValid = getInstructionFromIndex(LII->start);
1527 prevStart = std::prev(LII)->start;
1537 LII->start = instrIdx.getRegSlot();
1552 } else if (LII->start != instrIdx.getRegSlot()) {
lib/CodeGen/LiveRangeUtils.h 34 assert((SplitLRs[eq-1]->empty() || SplitLRs[eq-1]->expiredAt(I->start)) &&
lib/CodeGen/MachineScheduler.cpp 1742 GlobalSegment->start)) {
1747 if (SlotIndex::isSameInstr(std::prev(GlobalSegment)->start,
1753 assert(std::prev(GlobalSegment)->start < LocalLI->beginIndex() &&
1756 MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
lib/CodeGen/MachineVerifier.cpp 2477 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2485 if (S.start != MBBStartIdx && S.start != VNI->def) {
2485 if (S.start != MBBStartIdx && S.start != VNI->def) {
2506 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2529 if (!SlotIndex::isSameInstr(S.start, S.end)) {
2539 if (I+1 == LR.end() || (I+1)->start != S.end) {
2605 if (S.start == VNI->def && !VNI->isPHIDef()) {
lib/CodeGen/RegAllocGreedy.cpp 2208 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
2209 while (Uses[Gap+1].getBoundaryIndex() < I->start)
lib/CodeGen/RegAllocPBQP.cpp 261 return std::get<0>(I)->segments[std::get<1>(I)].start;
lib/CodeGen/RegisterCoalescer.cpp 625 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
645 if (SS != S.end() && SlotIndex::isSameInstr(SS->start, SS->end)) {
697 LiveInterval::iterator BI = llvm::upper_bound(IntB, ASeg.start);
700 for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
703 if (BI->start <= ASeg.start && BI->end > ASeg.start)
703 if (BI->start <= ASeg.start && BI->end > ASeg.start)
703 if (BI->start <= ASeg.start && BI->end > ASeg.start)
705 if (BI->start > ASeg.start && BI->start < ASeg.end)
705 if (BI->start > ASeg.start && BI->start < ASeg.end)
705 if (BI->start > ASeg.start && BI->start < ASeg.end)
728 LiveRange::Segment Added = LiveRange::Segment(S.start, S.end, DstValNo);
961 if (S->start.getBaseIndex() == CopyIdx.getBaseIndex())
2799 << OtherI->valno->id << '@' << OtherI->start << '\n');
2803 << OtherI->valno->id << '@' << OtherI->start << " to "
2811 if (++OtherI == Other.LR.end() || OtherI->start >= MBBEnd)
3162 if (I->start > Def)
3163 ED = ED.isValid() ? std::min(ED, I->start) : I->start;
3163 ED = ED.isValid() ? std::min(ED, I->start) : I->start;
lib/CodeGen/RegisterPressure.cpp 1271 return S != nullptr && S->start < Pos.getRegSlot(true) &&
lib/CodeGen/SplitKit.cpp 226 LIS.getMBBFromIndex(LVI->start)->getIterator();
253 BI.LiveIn = LVI->start <= Start;
257 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
258 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
266 if (++LVI == LVE || LVI->start >= Stop) {
272 if (LastStop < LVI->start) {
285 BI.FirstInstr = BI.FirstDef = LVI->start;
289 assert(LVI->start == LVI->valno->def && "Dangling Segment start");
291 BI.FirstDef = LVI->start;
306 if (LVI->start < Stop)
309 MFI = LIS.getMBBFromIndex(LVI->start)->getIterator();
326 LIS.getMBBFromIndex(LVI->start)->getIterator();
336 } while (Stop <= LVI->start);
347 if (I != Orig.end() && I->start <= Idx)
348 return I->start == Idx;
1129 SlotIndex Start = S.start;
lib/CodeGen/TwoAddressInstructionPass.cpp 258 if (I != LI.end() && I->start < MBBEndIdx)
878 if (I != LI.end() && I->start < MBBEndIdx)
1068 if (I != LI.end() && I->start < MBBEndIdx)
lib/CodeGen/VirtRegMap.cpp 279 if (!First.isValid() || SR.segments.front().start < First)
280 First = SR.segments.front().start;
300 if (SRI->start <= MBBBegin)
333 I = Indexes->advanceMBBIndex(I, Seg.start);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 599 SlotIndex Next = S->start.getBaseIndex();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 340 if (NextI != E && NextI->start.isRegister()) {
341 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
416 if (!Seg.start.isRegister())
418 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
421 PredDefs.push_back(Seg.start);
470 if (!Seg.start.isRegister())
472 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
487 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
487 if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
489 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
1112 if (!LR.start.isRegister())
1172 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
lib/Target/Hexagon/HexagonRegisterInfo.cpp 256 for (SlotIndex I = S.start.getBaseIndex(), E = S.end.getBaseIndex();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 306 NewFMAInt.getNextValue(AI->start,
309 NewFMAInt.addSegment(LiveInterval::Segment(AI->start, AI->end,
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 628 I->start = TeeIdx;