reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  579       BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
  635   MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);

lib/CodeGen/TargetInstrInfo.cpp

  838       BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
  842       BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)

lib/Target/AArch64/AArch64InstrInfo.cpp

 4021     MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
 4026     MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
 4032     MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
 4086       BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
 4182           BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
 4216         BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
 4273           BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
 4540         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f16), NewVR)
 4587         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv8f16), NewVR)
 4647         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f32), NewVR)
 4667         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f32), NewVR)
 4687         BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f64), NewVR)
 5665     Save = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), Reg)
 5669     Restore = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), AArch64::LR)

lib/Target/AMDGPU/SIInstrInfo.cpp

 1512     Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
 1516     Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
 1520     MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
 6077         BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_IF), DstReg)
 6105         BuildMI(*(MF), Branch->getDebugLoc(), get(TargetOpcode::PHI), DstReg);
 6121     MachineInstr *SIIFBREAK = BuildMI(*(MF), Branch->getDebugLoc(),

lib/Target/ARM/ARMBaseInstrInfo.cpp

  190       UpdateMI = BuildMI(MF, MI.getDebugLoc(),
  199       UpdateMI = BuildMI(MF, MI.getDebugLoc(),
  208       UpdateMI = BuildMI(MF, MI.getDebugLoc(),
  221       UpdateMI = BuildMI(MF, MI.getDebugLoc(),
  228       UpdateMI = BuildMI(MF, MI.getDebugLoc(),
  242           BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
  258           BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())

lib/Target/Hexagon/HexagonStoreWidening.cpp

  445     MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)

lib/Target/MSP430/MSP430FrameLowering.cpp

  248             BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
  256           New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri),
  276           BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)

lib/Target/Mips/MipsBranchExpansion.cpp

  487           BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
  598           BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)

lib/Target/NVPTX/NVPTXPeephole.cpp

  112       BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),

lib/Target/PowerPC/PPCFrameLowering.cpp

 2245         CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
 2288     MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
 2296     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
 2300     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
 2304     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)

lib/Target/PowerPC/PPCInstrInfo.cpp

 1261   NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),

lib/Target/X86/X86FixupBWInsts.cpp

  288       BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
  323       BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
  351       BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);

lib/Target/X86/X86FrameLowering.cpp

 1294         MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
 1297         MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),

lib/Target/X86/X86InstrInfo.cpp

 5510     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);

lib/Target/XCore/XCoreFrameLowering.cpp

  522         New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode), XCore::SP)