|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineInstrBuilder.h 53 DefineNoRead = Define | Undef,
97 flags & RegState::Undef,
483 return B ? RegState::Undef : 0;
lib/CodeGen/MIRParser/MIParser.cpp 1305 Flags |= RegState::Undef;
1471 Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef,
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 625 .addReg(AArch64::LR, RegState::Undef);
lib/Target/AArch64/AArch64InstrInfo.cpp 2483 .addReg(SrcRegX, RegState::Undef)
2510 .addReg(SrcRegX, RegState::Undef)
5616 .addReg(AArch64::LR, RegState::Undef);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1772 MIB.addReg(IfSourceRegister, RegState::Undef);
lib/Target/AMDGPU/GCNDPPCombine.cpp 181 DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 899 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill);
1130 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
lib/Target/AMDGPU/SIFoldOperands.cpp 720 B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 142 S |= RegState::Undef;
378 S &= ~(RegState::Undef | RegState::Dead);
lib/Target/AMDGPU/SIFrameLowering.cpp 772 .addReg(Spill[0].VGPR, RegState::Undef);
lib/Target/AMDGPU/SIISelLowering.cpp 3418 .addReg(SrcReg, RegState::Undef, SubReg)
3424 .addReg(SrcReg, RegState::Undef, SubReg)
3447 .addReg(SrcReg, RegState::Undef, SubReg)
3453 .addReg(SrcReg, RegState::Undef, SubReg)
3525 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3559 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
lib/Target/AMDGPU/SIInsertSkips.cpp 170 .addReg(AMDGPU::VGPR0, RegState::Undef)
171 .addReg(AMDGPU::VGPR0, RegState::Undef)
172 .addReg(AMDGPU::VGPR0, RegState::Undef)
173 .addReg(AMDGPU::VGPR0, RegState::Undef)
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1169 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
1598 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
lib/Target/AMDGPU/SIInstrInfo.cpp 1489 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1493 RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1599 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 1113 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
lib/Target/AMDGPU/SIRegisterInfo.cpp 809 .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef);
lib/Target/ARM/ARMBaseInstrInfo.cpp 816 MIB.addReg(DestReg, RegState::Undef);
4981 .addReg(DReg, RegState::Undef)
lib/Target/ARM/ARMExpandPseudoInsts.cpp 1581 .addReg(ARM::CPSR, RegState::Undef);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 637 unsigned DstState = RegState::Define | (ReadUndef ? RegState::Undef : 0);
885 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
lib/Target/Hexagon/HexagonInstrInfo.cpp 1137 .addReg(Reg, RegState::Undef)
1138 .addReg(Reg, RegState::Undef);
1145 .addReg(Reg, RegState::Undef)
1146 .addReg(Reg, RegState::Undef);
1152 .addReg(Hexagon::V0, RegState::Undef)
1153 .addReg(Hexagon::V0, RegState::Undef);
1159 .addReg(Hexagon::V0, RegState::Undef)
1160 .addReg(Hexagon::V0, RegState::Undef);
1167 .addReg(Vd, RegState::Undef)
1168 .addReg(Vd, RegState::Undef);
4275 PredRegFlags |= RegState::Undef;
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 56 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
134 .addUse(Mips::RA_64, RegState::Undef)
142 .addUse(Mips::RA, RegState::Undef)
lib/Target/Mips/MipsSEInstrInfo.cpp 683 .addReg(Mips::RA_64, RegState::Undef);
686 .addReg(Mips::RA, RegState::Undef);
lib/Target/PowerPC/PPCRegisterInfo.cpp 787 .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
lib/Target/SystemZ/SystemZInstrInfo.cpp 267 .addReg(DestReg, RegState::Undef)
lib/Target/X86/X86FixupBWInsts.cpp 324 .addReg(NewSrcReg, RegState::Undef)
lib/Target/X86/X86FrameLowering.cpp 650 .addReg(ZeroReg, RegState::Undef)
651 .addReg(ZeroReg, RegState::Undef);
lib/Target/X86/X86ISelLowering.cpp30441 .addReg(ZReg, RegState::Undef)
30442 .addReg(ZReg, RegState::Undef);
30691 .addReg(ZReg, RegState::Undef)
30692 .addReg(ZReg, RegState::Undef);
lib/Target/X86/X86InstrInfo.cpp 746 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
3885 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3885 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3902 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3902 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3914 .addReg(Reg, RegState::Undef)
3915 .addReg(Reg, RegState::Undef);
4012 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4168 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4168 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4169 .addReg(Reg, RegState::Undef).addImm(0xff);
4183 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4184 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4184 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4579 .addReg(Reg, RegState::Undef)
4580 .addReg(Reg, RegState::Undef);
4587 .addReg(XReg, RegState::Undef)
4588 .addReg(XReg, RegState::Undef)
4596 .addReg(XReg, RegState::Undef)
4597 .addReg(XReg, RegState::Undef)
4602 .addReg(Reg, RegState::Undef)
4603 .addReg(Reg, RegState::Undef);
lib/Target/X86/X86WinAllocaExpander.cpp 221 .addReg(RegA, RegState::Undef);
235 .addReg(RegA, RegState::Undef);