reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/ScheduleDAG.h

  101     SDep() : Dep(nullptr, Data) {}
  116       case Data:
  162       return getKind() != Data;
  212       return getKind() == Data && Contents.Reg != 0;
  219       assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
  229       assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
  469     case Data:

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  898                 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
  911                        (P->getKind() == SDep::Data) &&
  931             if (K != SDep::Data && K != SDep::Output && K != SDep::Anti)

lib/CodeGen/CriticalAntiDepBreaker.cpp

  582                     (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {

lib/CodeGen/MachinePipeliner.cpp

  803             SDep Dep(SU, SDep::Data, Reg);
 1307       else if (DepKind == SDep::Data && !TmpMI->isPHI() && TmpSU->NumPreds > 0)
 1319         if (Dep.getKind() != SDep::Data)
 2391         if (S.getKind() == SDep::Data && S.getSUnit()->getInstr()->isPHI())

lib/CodeGen/MachineScheduler.cpp

 1771     if (Succ.getKind() != SDep::Data || Succ.getReg() != LocalReg)
 3262     if (Dep.getKind() != SDep::Data ||

lib/CodeGen/ScheduleDAG.cpp

   77   case Data:   dbgs() << "Data"; break;
   84   case Data:
  138   if (D.getKind() == SDep::Data) {
  189   if (P.getKind() == SDep::Data) {
  333     if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth)

lib/CodeGen/ScheduleDAGInstrs.cpp

  261         Dep = SDep(SU, SDep::Data, *Alias);
  439         SDep Dep(SU, SDep::Data, Reg);
 1275       if (PredDep.getKind() != SDep::Data)
 1355     assert(PredDep.getKind() == SDep::Data && "Subtrees are for data edges");
 1367       if (SuccDep.getKind() == SDep::Data) {
 1433     if (SuccDep.getKind() == SDep::Data &&
 1460         if (PredDep.getKind() != SDep::Data

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  409   SDep FromDep(SU, SDep::Data, Reg);
  412   SDep ToDep(CopyFromSU, SDep::Data, 0);

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

 1115   SDep D(LoadSU, SDep::Data, 0);
 1257   SDep FromDep(SU, SDep::Data, Reg);
 1260   SDep ToDep(CopyFromSU, SDep::Data, 0);

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

  504           : SDep(OpSU, SDep::Data, PhysReg);
  648   if (dep.getKind() != SDep::Data)

lib/Target/AMDGPU/GCNMinRegStrategy.cpp

  187         S.getKind() != SDep::Data)

lib/Target/AMDGPU/SIMachineScheduler.cpp

  673         PredDep.getKind() == llvm::SDep::Data)

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  310   if (DepType == SDep::Data) {
  320   return DepType == SDep::Data || DepType == SDep::Anti ||
  371   assert(DepType == SDep::Data);
  453   assert(DepType == SDep::Data);
  527         (PI.getKind() != SDep::Data || PI.getReg() != Reg))
  997         if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data &&
 1420     if (DepType == SDep::Data) {
 1432     if (DepType == SDep::Data) {
 1439     if (DepType == SDep::Data && HII->isDotCurInst(J)) {
 1445     if (DepType == SDep::Data) {
 1491     if (I.isConditionalBranch() && DepType != SDep::Data &&
 1555     if (DepType == SDep::Data && J.getOpcode() == Hexagon::S2_allocframe) {