|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachinePipeliner.h 333 for (const SDep &Succ : Nodes[i]->Succs)
include/llvm/CodeGen/ScheduleDAG.h 440 for (const SDep &Succ : Succs)
lib/CodeGen/AggressiveAntiDepBreaker.cpp 929 for (SDep S : PathSU->Succs) {
lib/CodeGen/LatencyPriorityQueue.cpp 77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
93 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
93 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
lib/CodeGen/MachinePipeliner.cpp 611 for (auto &SI : SU->Succs) {
1148 for (auto &SI : SUnits[i].Succs) {
1318 for (auto &Dep : (*I)->Succs) {
1407 for (SUnit::const_succ_iterator IS = SU->Succs.begin(),
1408 ES = SU->Succs.end();
1461 for (SUnit::const_succ_iterator IS = (*I)->Succs.begin(),
1462 ES = (*I)->Succs.end();
1484 for (SUnit::succ_iterator SI = (*I)->Succs.begin(), SE = (*I)->Succs.end();
1484 for (SUnit::succ_iterator SI = (*I)->Succs.begin(), SE = (*I)->Succs.end();
1522 for (auto &SI : Cur->Succs)
1742 for (auto &SI : SU->Succs) {
1832 if (N->Succs.size() == 0)
1871 for (const auto &I : maxHeight->Succs) {
1930 for (const auto &I : maxDepth->Succs) {
2376 for (const auto &SI : SuccSU->Succs)
2390 for (auto &S : P.getSUnit()->Succs)
2434 for (unsigned i = 0, e = (unsigned)SU->Succs.size(); i != e; ++i) {
2435 if (SU->Succs[i].getSUnit() == I) {
2436 const SDep &Dep = SU->Succs[i];
2526 for (auto &S : SU->Succs) {
2649 for (auto &SI : SU.Succs)
2714 for (SDep &SuccEdge : SU->Succs) {
lib/CodeGen/MachineScheduler.cpp 646 for (SDep &Succ : SU->Succs)
1583 for (const SDep &Succ : SUa->Succs) {
1770 for (const SDep &Succ : LastLocalSU->Succs) {
3257 SmallVectorImpl<SDep> &Deps = isTop ? SU->Preds : SU->Succs;
3266 if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
3696 || Node->Succs.size() > ViewMISchedCutoff);
lib/CodeGen/MacroFusion.cpp 43 for (SDep &SI : FirstSU.Succs)
60 for (SDep &SI : FirstSU.Succs)
77 for (const SDep &SI : FirstSU.Succs) {
103 if (SU.Succs.empty())
lib/CodeGen/PostRASchedulerList.cpp 489 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
489 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
lib/CodeGen/ScheduleDAG.cpp 122 for (SDep &SuccDep : PredSU->Succs) {
167 N->Succs.push_back(P);
184 SmallVectorImpl<SDep>::iterator Succ = llvm::find(N->Succs, P);
185 assert(Succ != N->Succs.end() && "Mismatching preds / succs lists!");
186 N->Succs.erase(Succ);
224 for (SDep &SuccDep : SU->Succs) {
303 for (const SDep &SuccDep : Cur->Succs) {
376 if (SU.Succs.size() > 0) {
378 for (const SDep &Dep : SU.Succs) {
482 unsigned Degree = SU.Succs.size();
488 assert(SU.Succs.empty() && "SUnit should have no successors");
581 : make_range(SU->Succs.rbegin(), SU->Succs.rend())) {
581 : make_range(SU->Succs.rbegin(), SU->Succs.rend())) {
622 for (int I = SU->Succs.size()-1; I >= 0; --I) {
623 const SUnit *Succ = SU->Succs[I].getSUnit();
lib/CodeGen/ScheduleDAGInstrs.cpp 1366 for (const SDep &SuccDep : PredSU->Succs) {
1432 for (const SDep &SuccDep : SU->Succs) {
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 107 for (const SDep &Succ : SU->Succs) {
144 for (const SDep &Succ : SU->Succs)
229 for (const SDep &Succ : SU->Succs)
268 for (const SDep &Succ : Packet[i]->Succs) {
513 for (const SDep &Succ : SU->Succs) {
530 HorizontalVerticalBalance += (SU->Succs.size() - numberCtrlDepsInSU(SU));
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 192 for (SDep &Succ : SU->Succs) {
291 for (SDep &Succ : SU->Succs) {
359 for (SDep &Succ : SU->Succs) {
395 for (SDep &Succ : SU->Succs) {
533 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 770 for (SDep &Succ : SU->Succs) {
886 for (auto &Succ : SU->Succs) {
900 for (auto &Succ2 : SU->Succs) {
1070 for (SDep &Succ : SU->Succs) {
1198 for (SDep &Succ : SU->Succs) {
1237 for (SDep &Succ : SU->Succs) {
1604 assert(RootSU->Succs.empty() && "Graph root shouldn't have successors!");
2267 if (PredSU->NumSuccsLeft != PredSU->Succs.size())
2329 for (const SDep &Succ : SU->Succs) {
2380 for (const SDep &Succ : SU->Succs) {
2847 for (const SDep &Succ : SU->Succs) {
3007 for (const SDep &PredSucc : PredSU->Succs) {
3029 for (unsigned i = 0; i != PredSU->Succs.size(); ++i) {
3030 SDep Edge = PredSU->Succs[i];
3076 for (const SDep &Succ : DUSU->Succs) {
3091 while (SuccSU->Succs.size() == 1 &&
3095 SuccSU = SuccSU->Succs.front().getSUnit();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 798 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
799 EE = SU->Succs.end(); II != EE; ++II) {
lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp 139 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
139 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
lib/Target/AMDGPU/AMDGPUSubtarget.cpp 752 for (const SDep &SI : SUa->Succs) {
788 for (const SDep &SI : Succs[I]->Succs) {
827 for (SDep &SI : From->Succs) {
833 for (SDep &SI : SU->Succs) {
lib/Target/AMDGPU/GCNILPSched.cpp 109 for (const SDep &Succ : SU->Succs) {
lib/Target/AMDGPU/GCNMinRegStrategy.cpp 94 for (auto SDep : SU->Succs) {
110 return SU->Succs.size() - getReadySuccessors(SU);
185 for (const auto &S : SchedSU->Succs) {
221 for (const auto &S : SU->Succs) {
lib/Target/AMDGPU/R600Packetizer.cpp 194 for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
195 const SDep &Dep = SUJ->Succs[i];
lib/Target/AMDGPU/SIMachineScheduler.cpp 443 for (SDep& Succ : SU->Succs) {
484 for (SDep& Succ : SU->Succs) {
516 for (SDep& Succ : SU->Succs) {
869 for (SDep& SuccDep : SU->Succs) {
953 for (SDep& SuccDep : SU->Succs) {
1023 for (SDep& SuccDep : SU->Succs) {
1044 for (SDep& SuccDep : SU->Succs) {
1065 for (SDep& SuccDep : SU->Succs) {
1097 for (SDep& SuccDep : SU->Succs) {
1126 for (SDep& SuccDep : SU->Succs) {
1243 for (SDep& SuccDep : SU->Succs) {
1875 for (SDep& SuccDep : SU->Succs) {
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 143 for (auto &S : SU->Succs)
158 for (auto &S : SU->Succs)
lib/Target/Hexagon/HexagonMachineScheduler.cpp 70 if (SUd->Succs.size() == 0)
80 for (const auto &S : SUd->Succs) {
310 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
310 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
540 for (auto &Succ : SU->Succs) {
646 for (const SDep &SI : SU->Succs)
715 for (const SDep &SI : SU->Succs) {
740 for (const auto &SI : SU->Succs) {
836 CurrSize = (*I)->Succs.size();
837 CandSize = Candidate.SU->Succs.size();
lib/Target/Hexagon/HexagonSubtarget.cpp 152 for (SDep &SI : SU.Succs) {
348 MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
420 for (auto &I : Src->Succs) {
459 for (auto &I : Src->Succs) {
506 if (getZeroLatency(Dst, Dst->Succs) != nullptr)
515 DstBest = getZeroLatency(Src, Src->Succs);
562 for (auto &I : SrcBest->Succs)
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 927 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
928 auto &Dep = PacketSU->Succs[i];
991 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
992 auto Dep = PacketSU->Succs[i];
1395 for (unsigned i = 0; i < SUJ->Succs.size(); ++i) {
1399 if (SUJ->Succs[i].getSUnit() != SUI)
1402 SDep::Kind DepType = SUJ->Succs[i].getKind();
1421 DepReg = SUJ->Succs[i].getReg();
1428 if (!isCallDependent(I, DepType, SUJ->Succs[i].getReg()))