reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
70 return (*SUnits)[NodeNum].getHeight();
include/llvm/CodeGen/MachinePipeliner.h 234 unsigned getHeight(SUnit *Node) { return Node->getHeight(); }
include/llvm/CodeGen/MachineScheduler.h 716 return isTop() ? SU->getHeight() : SU->getDepth();
include/llvm/CodeGen/ResourcePriorityQueue.h 95 return (*SUnits)[NodeNum].getHeight();
lib/CodeGen/MachineScheduler.cpp1336 unsigned LiveOutHeight = DefSU->getHeight(); 1357 unsigned LiveInHeight = SU->getHeight() + DefSU->Latency; 2300 if (SU->getHeight() > BotLatency) { 2301 BotLatency = SU->getHeight(); 2618 Latency = Cand.SU->getHeight(); 2621 Latency = Cand.SU->getHeight(); 2688 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2688 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2692 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) { 2693 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2693 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),lib/CodeGen/ScheduleDAG.cpp
256 if (NewHeight <= getHeight()) 351 dbgs() << " Height : " << getHeight() << "\n"; 406 (isBottomUp ? SUnit.getHeight() : SUnit.getDepth()) >lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
406 ResCount += (SU->getHeight() * ScaleTwo); 420 ResCount += (SU->getHeight() * ScaleTwo);lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
185 assert(CurCycle >= SU->getHeight() && "Node scheduled below its height!"); 194 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) {lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
414 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); 422 unsigned Height = PredSU->getHeight(); 612 unsigned ReadyCycle = PendingQueue[i]->getHeight(); 662 unsigned ReadyCycle = SU->getHeight(); 741 if (CurCycle < SU->getHeight()) 742 LLVM_DEBUG(dbgs() << " Height [" << SU->getHeight() 836 LLVM_DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: "); 902 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) 902 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) 908 if (SU->getHeight() < MinAvailableCycle) 909 MinAvailableCycle = SU->getHeight(); 936 unsigned HazardCycle = (*I)->getHeight(); 939 for (; SU->getHeight() > HazardCycle; ++HazardCycle) { 953 CurCycle = OldSU->getHeight(); 1508 if (LiveRegGens[Reg]->getHeight() < LiveCycle) { 1510 LiveCycle = BtSU->getHeight(); 1907 dbgs() << "Height " << SU->getHeight() << ": "; 2331 unsigned Height = Succ.getSUnit()->getHeight(); 2477 int LHeight = (int)left->getHeight() + LPenalty; 2478 int RHeight = (int)right->getHeight() + RPenalty; 2613 if (left->getHeight() != right->getHeight()) 2613 if (left->getHeight() != right->getHeight()) 2614 return left->getHeight() > right->getHeight(); 2614 return left->getHeight() > right->getHeight(); 2658 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false; 2701 if (SU->getHeight() > CurCycle) return false; 2770 bool LStall = BUHasStall(left, left->getHeight(), SPQ); 2771 bool RStall = BUHasStall(right, right->getHeight(), SPQ); 2773 return left->getHeight() > right->getHeight(); 2773 return left->getHeight() > right->getHeight(); 2786 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) { 2786 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) { 2787 int spread = (int)left->getHeight() - (int)right->getHeight(); 2787 int spread = (int)left->getHeight() - (int)right->getHeight(); 2789 return left->getHeight() > right->getHeight(); 2789 return left->getHeight() > right->getHeight(); 3084 if (SuccSU->getHeight() < SU.getHeight() && 3084 if (SuccSU->getHeight() < SU.getHeight() && 3085 (SU.getHeight() - SuccSU->getHeight()) > 1) 3085 (SU.getHeight() - SuccSU->getHeight()) > 1)lib/Target/AMDGPU/GCNILPSched.cpp
111 unsigned Height = Succ.getSUnit()->getHeight(); 136 int LHeight = (int)left->getHeight(); 137 int RHeight = (int)right->getHeight(); 180 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) { 180 if (!DisableSchedHeight && left->getHeight() != right->getHeight()) { 181 int spread = (int)left->getHeight() - (int)right->getHeight(); 181 int spread = (int)left->getHeight() - (int)right->getHeight(); 183 return left->getHeight() > right->getHeight() ? right : left; 183 return left->getHeight() > right->getHeight() ? right : left; 229 if (left->getHeight() != right->getHeight()) 229 if (left->getHeight() != right->getHeight()) 230 return (left->getHeight() > right->getHeight()) ? right : left; 230 return (left->getHeight() > right->getHeight()) ? right : left; 260 if (C.SU->getHeight() <= CurCycle) { 283 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge.getLatency()); 320 return C1.SU->getHeight() < C2.SU->getHeight(); 320 return C1.SU->getHeight() < C2.SU->getHeight(); 322 advanceToCycle(std::max(CurCycle + 1, EarliestSU->getHeight())); 340 advanceToCycle(SU->getHeight());lib/Target/Hexagon/HexagonMachineScheduler.cpp
212 ++su) if (SUnits[su].getHeight() > maxH) maxH = 213 SUnits[su].getHeight(); 600 ResCount += (SU->getHeight() * ScaleTwo); 605 dbgstr << "h" << std::setw(3) << SU->getHeight() << "|";lib/Target/Hexagon/HexagonMachineScheduler.h
186 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth()); 212 unsigned PathLength = isTop() ? SU->getHeight() : SU->getDepth();lib/Target/SystemZ/SystemZMachineScheduler.cpp
188 dbgs() << " Height:" << c.SU->getHeight(); dbgs() << "\n";); 229 if (SU->getHeight() > other.SU->getHeight()) 229 if (SU->getHeight() > other.SU->getHeight()) 231 if (SU->getHeight() < other.SU->getHeight()) 231 if (SU->getHeight() < other.SU->getHeight())lib/Target/SystemZ/SystemZMachineScheduler.h
80 if (lhs->getHeight() > rhs->getHeight()) 80 if (lhs->getHeight() > rhs->getHeight()) 82 else if (lhs->getHeight() < rhs->getHeight()) 82 else if (lhs->getHeight() < rhs->getHeight())