reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/SelectionDAGNodes.h

  189   inline bool isMachineOpcode() const;

References

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  268   if (Op.isMachineOpcode() &&
  368   if (Op.isMachineOpcode()) {
  996     if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&

lib/Target/AMDGPU/R600ISelLowering.cpp

 2086   if (!Src.isMachineOpcode())

lib/Target/AMDGPU/SIISelLowering.cpp

10319     if ((Src0.isMachineOpcode() &&
10336     if (Src0.isMachineOpcode() &&
10338       if (Src1.isMachineOpcode() &&
10341       else if (Src2.isMachineOpcode() &&
10366     if (VDstIn.isMachineOpcode()

lib/Target/Hexagon/HexagonISelLowering.h

  358       if (Op.isMachineOpcode())

lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

 1443   assert(!Op.isMachineOpcode());

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 5663         if (Op.isMachineOpcode()) {
 5690         if (Op.isMachineOpcode()) {
 6063   if (!Op32.isMachineOpcode())
 6234     if (!ISR.isMachineOpcode() ||
 6245     if (!IDef.isMachineOpcode() ||
 6253     if (!Op32.isMachineOpcode())
 6433     if (!Base.isMachineOpcode())
 6501         if (!HBase.isMachineOpcode() ||

lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  252     if (!Base.isMachineOpcode() || Base.getMachineOpcode() != RISCV::ADDI)

lib/Target/X86/X86ISelDAGToDAG.cpp

 1128   if (!N0.isMachineOpcode() ||
 1137   if (!N00.isMachineOpcode() || N00.getMachineOpcode() != ExpectedOpc)
 1180         N->getOperand(0).isMachineOpcode()) {
 1227         N->getOperand(0).isMachineOpcode() &&
 1263     if (!Move.isMachineOpcode())
 1288     if (!In.isMachineOpcode() ||