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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/SelectionDAGNodes.h 300 return Val != V;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1208 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1678 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
2821 N0.getValue(1) != CarryIn)) &&
4093 if (HiOpt.getNode() && HiOpt != Hi &&
5406 if (N00 != N10)
5939 OppShiftLHS.getOperand(0) != ExtractFrom.getOperand(0) ||
6195 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
6536 else if (stripTruncAndExt(CombinedValue) != stripTruncAndExt(Value))
6702 else if (Chain != LChain)
6812 if (Other != Xor1)
12500 if (Dividend != FPOne) {
14119 if (Chain != BetterChain) {
14715 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
14882 if (LD->getBasePtr() != Ptr ||
15831 if (LoadNodes[i].MemNode->getChain() != FirstChain)
17988 if (Op.getOperand(0) != SingleSource)
18944 if (V->getOperand(i) != Base) {
19153 if (SV1.getNode() && SV1 != CurrentVec)
19768 if (LHS.getOperand(0) != RHS.getOperand(0) ||
20844 return ST->getOperand(0) != NewChain;
20881 if (St->getChain() != BetterChain) {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 520 if (Res && Res != SDValue(Node, 0))
632 if (Res && Res != SDValue(Node, 0))
1187 if (SAO != Op1)
1207 if (SAO != Op2)
1301 ST->getValue() != Vec)
1923 if (V != Value1)
1925 } else if (V != Value1 && V != Value2) {
1925 } else if (V != Value1 && V != Value2) {
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 506 } else if (Op != OrigOp) {
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 70 if (From != To)
260 if (Lowered != Result) {
286 if (Lowered != Result) {
509 if (Result != Op) {
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 191 if (N->getOperand(i) != NotZero && !N->getOperand(i).isUndef())
2265 if (Scl && Scl != Op)
4169 (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
4215 (IdentitySrc && Op.getOperand(0) != IdentitySrc) ||
9095 if (!Shuffle || Shuffle->getOperand(0) != Op)
9240 if (LD->getChain() != Base->getChain())
9446 } else if (Splatted != Op) {
lib/CodeGen/SelectionDAG/TargetLowering.cpp 2218 [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) {
3026 if (Y != N1)
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2052 if (UserNode->getOperand(1) != Orig)
2062 if (UserNode->getOperand(0) != Orig)
2069 if (UserNode->getOperand(0) != Orig)
lib/Target/AArch64/AArch64ISelLowering.cpp 7603 else if (ConstantValue != V)
7609 else if (V != Value)
10774 else if (StVal.getOperand(1) != SplatVal)
11921 if (Ptr != Base)
lib/Target/AMDGPU/SIISelLowering.cpp 4380 if (I.getUse().get() != Value)
8298 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
8302 if (X != LHS.getOperand(1))
8426 if (Src != RHS.getOperand(0))
9749 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) ||
9749 if (Idx1 != Op2.getOperand(1) || Idx2 != FMAOp2.getOperand(1) ||
lib/Target/AMDGPU/SIInstrInfo.cpp 164 if (Load0->getOperand(0) != Load1->getOperand(0))
195 if (Load0->getOperand(0) != Load1->getOperand(0))
lib/Target/ARM/ARMBaseInstrInfo.cpp 1889 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1890 Load1->getOperand(4) != Load2->getOperand(4))
1894 if (Load1->getOperand(3) != Load2->getOperand(3))
lib/Target/ARM/ARMISelDAGToDAG.cpp 3260 Subc.getOperand(1) != SmulLoHi.getValue(0) ||
3261 N->getOperand(1) != SmulLoHi.getValue(1) ||
3262 N->getOperand(2) != Subc.getValue(1))
lib/Target/ARM/ARMISelLowering.cpp 4777 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4777 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4778 V2TmpReg != V2)
4858 if (*K != KTmp || V != VTmp)
4858 if (*K != KTmp || V != VTmp)
6587 if (NewVal != SDValue()) {
6604 if (NewVal != SDValue()) {
7271 if (shuffle != SDValue())
11177 if (SRA.getOperand(0) != Mul)
11308 if ((AddeSubeOp0 != MULOp.getValue(1)) && (AddeSubeOp1 != MULOp.getValue(1)))
11308 if ((AddeSubeOp0 != MULOp.getValue(1)) && (AddeSubeOp1 != MULOp.getValue(1)))
12083 if (SRL.getOperand(0) != SDValue(SMULLOHI, 0) ||
12084 SHL.getOperand(0) != SDValue(SMULLOHI, 1))
12484 if (NewFrom != From) {
13992 if (Op0 != Y)
14281 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
15362 if (Ptr != Base) {
15370 if (Ptr != Base)
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 377 else if (SplatV != Words[i])
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 617 if (U->getOperand(0) != Vector)
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 1756 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
2079 if (VRI.V != BG.V)
2255 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
4285 else if (LHS != InnerLHS || RHS != InnerRHS)
4285 else if (LHS != InnerLHS || RHS != InnerRHS)
6509 if (HImmOpnd != ImmOpnd)
lib/Target/PowerPC/PPCISelLowering.cpp 2125 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2167 else if (OpVal != N->getOperand(i))
8220 if (V->getOperand(i) != Op0 ||
12664 if (N->getOperand(i) != FirstInput)
12879 if (Input && Input != Extract.getOperand(0))
12993 Ext1.getOperand(0) != Ext2.getOperand(0))
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1269 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1270 LoadNode->getOffset() != StoreNode->getOffset())
lib/Target/SystemZ/SystemZISelLowering.cpp 4589 else if (Elem != Single) {
4716 if (!Done[I] && !Elems[I].isUndef() && Elems[I] != ReplicatedVal)
lib/Target/X86/X86ISelDAGToDAG.cpp 2834 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
2835 LoadNode->getOffset() != StoreNode->getOffset())
3324 if (N1 != N01 || !checkTwoUse(N1))
3391 if (RealX != X && RealX.getOpcode() == ISD::SRL)
4158 bool CanFoldLoads = Src0 != Src1;
lib/Target/X86/X86ISelLowering.cpp 7261 if (UsedInputs[j] != Inputs[i])
7539 Op.getOperand(0) != Op.getOperand(1)) {
7601 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
8135 if (Op->getOperand(i) != ExtValue)
8454 else if (VecIn1 != ExtractedFromVec) {
8457 else if (VecIn2 != ExtractedFromVec)
8525 else if (In != Op.getOperand(SplatIdx))
8792 Op0.getOperand(1) != Op1.getOperand(1))
8819 if (InVec0 != Op0.getOperand(0)) {
8826 if (InVec0 != Op0.getOperand(0))
8830 if (InVec1 != Op1.getOperand(0))
8983 Op0.getOperand(0) != Op1.getOperand(0) ||
8999 if (SourceVec != Op0.getOperand(0))
9245 if (IsShift && any_of(RHSElts, [&](SDValue V) { return RHSElts[0] != V; }))
9554 else if (SrcVec != Op.getOperand(0))
9569 else if (IndicesVec != ExtractedIndex.getOperand(0))
9796 if (Ops[i % 2] != Op.getOperand(i))
10270 MaskBV->getOperand(Mask[i] % Size) !=
10570 if (V && V != SrcV)
10930 else if (V != (Mask[i] < Size ? V1 : V2))
11476 else if (TargetV != MaskV)
12146 } else if (InputV != V)
12446 N0.getOperand(0) != N1.getOperand(0))
16341 else if (Ops[OpIndex] != Op)
19672 LHS.getOperand(0) != RHS.getOperand(0) ||
25687 if (Vals[j] != Amt.getOperand(i + j))
33355 if (V.getOperand(0) != V.getOperand(1) ||
33597 if (N10 != N0)
33869 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
33869 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
33870 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
33870 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
33875 if ((V1->getOperand(0) != LHS || V1->getOperand(1) != RHS) &&
33875 if ((V1->getOperand(0) != LHS || V1->getOperand(1) != RHS) &&
33876 (V1->getOperand(0) != RHS || V1->getOperand(1) != LHS))
33876 (V1->getOperand(0) != RHS || V1->getOperand(1) != LHS))
33917 FMAdd.getOperand(0) != FMSub.getOperand(0) || !FMAdd.hasOneUse() ||
33918 FMAdd.getOperand(1) != FMSub.getOperand(1) || !FMSub.hasOneUse() ||
33919 FMAdd.getOperand(2) != FMSub.getOperand(2))
34045 HOp.getOperand(0) != HOp.getOperand(1))
34293 Use->getOperand(0) != Amt;
37501 SetCC0->getOperand(1) != SetCC1->getOperand(1))
38664 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
40859 if (A != C) {
41333 if (ZExtIn != N00In || SExtIn != N01In ||
41333 if (ZExtIn != N00In || SExtIn != N01In ||
41334 ZExtIn != N10In || SExtIn != N11In)
41334 ZExtIn != N10In || SExtIn != N11In)
43907 if (Mul != Op0L->getOperand(0) || Mul != Op1L->getOperand(0) ||
43907 if (Mul != Op0L->getOperand(0) || Mul != Op1L->getOperand(0) ||
43908 Mul != Op0H->getOperand(0) || Mul != Op1H->getOperand(0))
43908 Mul != Op0H->getOperand(0) || Mul != Op1H->getOperand(0))
44035 if (In0 != N00In)
44037 if (In0 != N10In)
44039 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In)
44039 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In)
44039 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In)
44039 if (In0 != N00In || In1 != N01In || In0 != N10In || In1 != N11In)
44645 if (InVec != InVecBC && InVecBCVT.isVector()) {