reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/ADT/IntervalMap.h

  172     return b <= x;

include/llvm/CodeGen/LiveInterval.h

  176         return start <= I && I < end;
  182         return (start <= S && S < end) && (start < E && E <= end);
  182         return (start <= S && S < end) && (start < E && E <= end);
  266       while (I->end <= Pos) ++I;
  274       while (I->end <= Pos) ++I;
  394       return r != end() && r->start <= index;
  429       return I != end() && I->start <= Idx ? I : end();
  434       return I != end() && I->start <= Idx ? I : end();
  546       if (I->start <= Idx.getBaseIndex()) {
  602                   return Begin <= Idx && Idx < End;
  627         if (Seg->end <= *Idx) {

include/llvm/CodeGen/SlotIndexes.h

  527       assert(J != MBBIndexEnd() && J->first <= index &&

lib/CodeGen/LiveDebugVariables.cpp

  740   if (I.valid() && I.start() <= Start) {
  818       if (I.valid() && I.start() <= Idx)

lib/CodeGen/LiveInterval.cpp

  128     if (I->end <= StartIdx)
  144     if (I->end <= StartIdx)
  173     if (MergeTo != segments().end() && MergeTo->start <= I->end &&
  201     } while (NewStart <= MergeTo->start);
  228         if (B->start <= Start && B->end >= Start) {
  235         assert(B->end <= Start &&
  245         if (I->start <= End) {
  412   assert((StartPos->start <= i->start || StartPos == other.begin()) &&
  420     if (StartPos != other.end() && StartPos->start <= i->start) {
  560   assert(segments.empty() || segments.back().end <= S.start);
 1069       assert(I->end <= std::next(I)->start);
 1161   assert(A.start <= B.start && "Unordered live segments.");
 1194   if (ReadI != E && ReadI->end <= Seg.start) {
 1202       while (ReadI != E && ReadI->end <= Seg.start)
 1209   if (ReadI != E && ReadI->start <= Seg.start) {

lib/CodeGen/LiveIntervalUnion.cpp

  163     assert(LRI->end <= LiveUnionI.start() && "Expected non-overlap");

lib/CodeGen/LiveIntervals.cpp

 1464   assert(getMBBStartIdx(MI.getParent()) <= OldIndex &&

lib/CodeGen/RegAllocGreedy.cpp

 1214       if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
 1290     if (Intf.first() <= Indexes->getMBBStartIdx(Number))

lib/CodeGen/RegAllocPBQP.cpp

  348              (getEndPoint(*RetireItr) <= getStartPoint(Cur))) {

lib/CodeGen/RegisterCoalescer.cpp

  703       if (BI->start <= ASeg.start && BI->end > ASeg.start)
 2647   if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)

lib/CodeGen/RegisterPressure.cpp

  195   if (TopIdx <= NextTop)

lib/CodeGen/SplitKit.cpp

  253       BI.LiveIn = LVI->start <= Start;
  336     } while (Stop <= LVI->start);
  347   if (I != Orig.end() && I->start <= Idx)
 1136       } else if (AssignI.start() <= Start) {
 1184         if (BlockEnd <= End)
 1193       assert(Start <= BlockStart && "Expected live-in block");
 1627     assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
 1679     assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
 1690   assert(LeaveBefore <= EnterAfter && "Missed case");
 1700   assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
 1748       assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
 1755       assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
 1778     assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
 1793   assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
 1813   if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {

lib/CodeGen/VirtRegMap.cpp

  288        MBBI != Indexes->MBBIndexEnd() && MBBI->first <= Last; ++MBBI) {
  296       while (SRI != SR->end() && SRI->end <= MBBBegin)
  300       if (SRI->start <= MBBBegin)

lib/Target/AMDGPU/SIMachineScheduler.cpp

  319     if (InstSlot >= First && InstSlot <= Last)