reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc

20061   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

47919   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc

12181   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

15649   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/AVR/AVRGenRegisterInfo.inc

 1565   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/BPF/BPFGenRegisterInfo.inc

  590   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 3526   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc

  813   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc

  523   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 7142   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc

 5502   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc

 1694   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/Sparc/SparcGenRegisterInfo.inc

 2661   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc

 2820   return TV ? getRegClass(TV - 1) : nullptr;

gen/lib/Target/X86/X86GenRegisterInfo.inc

 9595   return TV ? getRegClass(TV - 1) : nullptr;

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

  576           &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum)) !=
  958                                     *TRI.getRegClass(RCEnum), TII, TRI, RBI);

lib/CodeGen/GlobalISel/RegisterBank.cpp

   34     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
   45       const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
  104     const TargetRegisterClass &RC = *TRI->getRegClass(RCId);

lib/CodeGen/MIRParser/MIParser.cpp

  280     const auto *RC = TRI->getRegClass(I);

lib/CodeGen/MachineInstr.cpp

  861     return TRI->getRegClass(RCID);
 1635           OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  615     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
  632   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  334       const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);

lib/CodeGen/TargetInstrInfo.cpp

   60   return TRI->getRegClass(RegClass);

lib/CodeGen/TargetLoweringBase.cpp

 1150     const TargetRegisterClass *SuperRC = TRI->getRegClass(i);

lib/CodeGen/TargetRegisterInfo.cpp

  179     const TargetRegisterClass *SubRC = getRegClass(It.getID());
  244       return TRI->getRegClass(I + countTrailingZeros(Common));

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

  519   auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

  952   bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
  955           TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

   67   assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
   73   assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
   75   assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
   80   assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1859     return AMDGPURegisterInfo::getRegClass(RCID);

lib/Target/ARM/ARMAsmPrinter.cpp

  374           ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {

lib/Target/ARM/ARMRegisterBankInfo.cpp

  149   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
  151   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&
  153   assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&
  155   assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&
  157   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&
  159   assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&
  161   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) &&
  163   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPREven_and_tGPR_and_tcGPRRegClassID)) &&
  165   assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&

lib/Target/ARM/Thumb1FrameLowering.cpp

  678       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
  689       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));

lib/Target/AVR/AVRRegisterInfo.cpp

  283   if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {

lib/Target/Mips/MipsISelLowering.cpp

 3893     RC = TRI->getRegClass(Prefix == "hi" ?
 3917     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
 3937     RC = TRI->getRegClass(Mips::FCCRegClassID);

lib/Target/Mips/MipsInstructionSelector.cpp

  376       DefRC = TRI.getRegClass(DestReg);

lib/Target/NVPTX/NVPTXAsmPrinter.cpp

 1674     const TargetRegisterClass *RC = TRI->getRegClass(i);

lib/Target/X86/X86RegisterBankInfo.cpp

   38   assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) &&