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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/TargetInstrInfo.h 60 class TargetSchedModel;
include/llvm/CodeGen/TargetSubtargetInfo.h 53 class TargetSchedModel;
References
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc17972 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
17998 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc 786 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
812 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/AMDGPU/R600GenSubtargetInfo.inc 310 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
339 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/ARC/ARCGenSubtargetInfo.inc 136 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
162 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc19572 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
19601 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/AVR/AVRGenSubtargetInfo.inc 537 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
563 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/BPF/BPFGenSubtargetInfo.inc 159 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
185 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/Hexagon/HexagonGenSubtargetInfo.inc 4683 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
4713 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/Lanai/LanaiGenSubtargetInfo.inc 217 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
246 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/MSP430/MSP430GenSubtargetInfo.inc 160 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
186 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/Mips/MipsGenSubtargetInfo.inc 3863 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
3889 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc 235 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
261 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/PowerPC/PPCGenSubtargetInfo.inc 8212 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
8241 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 273 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
300 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/Sparc/SparcGenSubtargetInfo.inc 529 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
558 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/SystemZ/SystemZGenSubtargetInfo.inc 5174 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
5200 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc 178 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
204 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/X86/X86GenSubtargetInfo.inc21497 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
21526 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
gen/lib/Target/XCore/XCoreGenSubtargetInfo.inc 137 unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
163 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
include/llvm/CodeGen/MachineScheduler.h 598 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
614 const TargetSchedModel *SchedModel = nullptr;
692 void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel,
880 const TargetSchedModel *SchedModel);
885 const TargetSchedModel *SchedModel = nullptr;
include/llvm/CodeGen/MachineTraceMetrics.h 93 TargetSchedModel SchedModel;
include/llvm/CodeGen/ScheduleDAGInstrs.h 125 TargetSchedModel SchedModel;
262 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
include/llvm/CodeGen/TargetInstrInfo.h 1468 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1478 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
include/llvm/CodeGen/TargetSubtargetInfo.h 141 const TargetSchedModel *SchedModel) const {
lib/CodeGen/EarlyIfConversion.cpp 940 TargetSchedModel SchedModel;
lib/CodeGen/IfConversion.cpp 188 TargetSchedModel SchedModel;
lib/CodeGen/MachineCombiner.cpp 70 TargetSchedModel TSchedModel;
lib/CodeGen/MachineLICM.cpp 99 TargetSchedModel SchedModel;
lib/CodeGen/MachineScheduler.cpp 1887 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
1896 for (TargetSchedModel::ProcResIter
1907 init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem) {
2263 for (TargetSchedModel::ProcResIter
2276 for (TargetSchedModel::ProcResIter
2450 const TargetSchedModel *SchedModel) {
2455 for (TargetSchedModel::ProcResIter
lib/CodeGen/MachineTraceMetrics.cpp 125 for (TargetSchedModel::ProcResIter
894 const TargetSchedModel &SchedModel,
954 const TargetSchedModel &SchedModel,
1240 for (TargetSchedModel::ProcResIter
lib/CodeGen/TargetInstrInfo.cpp 1111 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 71 TargetSchedModel SchedModel;
lib/Target/AArch64/AArch64StorePairSuppress.cpp 34 TargetSchedModel SchedModel;
lib/Target/AMDGPU/AMDGPUSubtarget.cpp 848 const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel();
lib/Target/AMDGPU/GCNHazardRecognizer.h 50 TargetSchedModel TSchedModel;
lib/Target/ARM/ARMBaseInstrInfo.cpp 4694 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4715 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
lib/Target/ARM/ARMBaseInstrInfo.h 388 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
393 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
lib/Target/Hexagon/HexagonMachineScheduler.h 41 const TargetSchedModel *SchedModel;
51 VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
135 const TargetSchedModel *SchedModel = nullptr;
165 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
218 const TargetSchedModel *SchedModel = nullptr;
lib/Target/PowerPC/PPCInstrInfo.h 223 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
lib/Target/PowerPC/PPCTargetTransformInfo.cpp 501 TargetSchedModel SchedModel;
lib/Target/SystemZ/SystemZHazardRecognizer.cpp 175 for (TargetSchedModel::ProcResIter
296 for (TargetSchedModel::ProcResIter
400 for (TargetSchedModel::ProcResIter
lib/Target/SystemZ/SystemZHazardRecognizer.h 48 const TargetSchedModel *SchedModel;
111 const TargetSchedModel *SM)
lib/Target/SystemZ/SystemZMachineScheduler.h 38 TargetSchedModel SchedModel;
lib/Target/X86/X86CmovConversion.cpp 117 TargetSchedModel TSchedModel;
lib/Target/X86/X86FixupLEAs.cpp 115 TargetSchedModel TSM;
lib/Target/X86/X86InstrInfo.h 451 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
lib/Target/X86/X86PadShortFunction.cpp 84 TargetSchedModel TSM;