|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 6466 Inst.setOpcode(Opcode);
27538 Inst.setOpcode(it->Opcode);
gen/lib/Target/AArch64/AArch64GenDisassemblerTables.inc25811 MI.setOpcode(Opc);
25835 TmpMI.setOpcode(Opc);
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc 3789 Inst.setOpcode(Opcode);
24066 Inst.setOpcode(it->Opcode);
gen/lib/Target/AMDGPU/AMDGPUGenDisassemblerTables.inc42075 MI.setOpcode(Opc);
42099 TmpMI.setOpcode(Opc);
gen/lib/Target/AMDGPU/AMDGPUGenMCPseudoLowering.inc 17 TmpInst.setOpcode(AMDGPU::V_MOV_B32_e32_vi);
gen/lib/Target/ARC/ARCGenDisassemblerTables.inc 1546 MI.setOpcode(Opc);
1570 TmpMI.setOpcode(Opc);
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 4350 Inst.setOpcode(Opcode);
15220 Inst.setOpcode(it->Opcode);
gen/lib/Target/ARM/ARMGenDisassemblerTables.inc21853 MI.setOpcode(Opc);
21877 TmpMI.setOpcode(Opc);
gen/lib/Target/ARM/ARMGenMCPseudoLowering.inc 17 TmpInst.setOpcode(ARM::Bcc);
30 TmpInst.setOpcode(ARM::LDMIA_UPD);
55 TmpInst.setOpcode(ARM::MLA);
82 TmpInst.setOpcode(ARM::MOVr);
99 TmpInst.setOpcode(ARM::MUL);
123 TmpInst.setOpcode(ARM::SMLAL);
156 TmpInst.setOpcode(ARM::SMULL);
183 TmpInst.setOpcode(ARM::Bcc);
196 TmpInst.setOpcode(ARM::BX);
206 TmpInst.setOpcode(ARM::MOVr);
223 TmpInst.setOpcode(ARM::UMLAL);
256 TmpInst.setOpcode(ARM::UMULL);
283 TmpInst.setOpcode(ARM::VMOVv2i32);
298 TmpInst.setOpcode(ARM::VMOVv4i32);
313 TmpInst.setOpcode(ARM::t2LDMIA_UPD);
338 TmpInst.setOpcode(ARM::tMOVr);
355 TmpInst.setOpcode(ARM::tBX);
369 TmpInst.setOpcode(ARM::tBX);
384 TmpInst.setOpcode(ARM::tBL);
399 TmpInst.setOpcode(ARM::tLDMIA);
421 TmpInst.setOpcode(ARM::tPOP);
440 TmpInst.setOpcode(ARM::t2B);
455 TmpInst.setOpcode(ARM::tB);
470 TmpInst.setOpcode(ARM::tBX);
gen/lib/Target/AVR/AVRGenAsmMatcher.inc 499 Inst.setOpcode(Opcode);
1391 Inst.setOpcode(it->Opcode);
gen/lib/Target/AVR/AVRGenDisassemblerTables.inc 668 MI.setOpcode(Opc);
692 TmpMI.setOpcode(Opc);
gen/lib/Target/BPF/BPFGenAsmMatcher.inc 271 Inst.setOpcode(Opcode);
1034 Inst.setOpcode(it->Opcode);
gen/lib/Target/BPF/BPFGenDisassemblerTables.inc 605 MI.setOpcode(Opc);
629 TmpMI.setOpcode(Opc);
gen/lib/Target/Hexagon/HexagonGenAsmMatcher.inc 2548 Inst.setOpcode(Opcode);
10380 Inst.setOpcode(it->Opcode);
gen/lib/Target/Hexagon/HexagonGenDisassemblerTables.inc12292 MI.setOpcode(Opc);
12316 TmpMI.setOpcode(Opc);
gen/lib/Target/Lanai/LanaiGenAsmMatcher.inc 347 Inst.setOpcode(Opcode);
1175 Inst.setOpcode(it->Opcode);
gen/lib/Target/Lanai/LanaiGenDisassemblerTables.inc 546 MI.setOpcode(Opc);
570 TmpMI.setOpcode(Opc);
gen/lib/Target/MSP430/MSP430GenAsmMatcher.inc 332 Inst.setOpcode(Opcode);
1233 Inst.setOpcode(it->Opcode);
gen/lib/Target/MSP430/MSP430GenDisassemblerTables.inc 1423 MI.setOpcode(Opc);
1447 TmpMI.setOpcode(Opc);
gen/lib/Target/Mips/MipsGenAsmMatcher.inc 1328 Inst.setOpcode(Opcode);
8209 Inst.setOpcode(it->Opcode);
gen/lib/Target/Mips/MipsGenDisassemblerTables.inc10403 MI.setOpcode(Opc);
10427 TmpMI.setOpcode(Opc);
gen/lib/Target/Mips/MipsGenMCPseudoLowering.inc 17 TmpInst.setOpcode(Mips::AND_V);
33 TmpInst.setOpcode(Mips::AND_V);
49 TmpInst.setOpcode(Mips::AND_V);
65 TmpInst.setOpcode(Mips::BEQ);
79 TmpInst.setOpcode(Mips::BGEZAL);
91 TmpInst.setOpcode(Mips::BGEZAL_MM);
103 TmpInst.setOpcode(Mips::BSEL_V);
122 TmpInst.setOpcode(Mips::BSEL_V);
141 TmpInst.setOpcode(Mips::BSEL_V);
160 TmpInst.setOpcode(Mips::BSEL_V);
179 TmpInst.setOpcode(Mips::BSEL_V);
198 TmpInst.setOpcode(Mips::BEQ_MM);
212 TmpInst.setOpcode(Mips::FMAX_A_D);
228 TmpInst.setOpcode(Mips::FMAX_A_W);
244 TmpInst.setOpcode(Mips::JALR);
256 TmpInst.setOpcode(Mips::JALR_HB64);
268 TmpInst.setOpcode(Mips::JALR_HB);
280 TmpInst.setOpcode(Mips::JALR);
292 TmpInst.setOpcode(Mips::BALC_MMR6);
302 TmpInst.setOpcode(Mips::SLL);
315 TmpInst.setOpcode(Mips::NOR_V);
331 TmpInst.setOpcode(Mips::NOR_V);
347 TmpInst.setOpcode(Mips::NOR_V);
363 TmpInst.setOpcode(Mips::OR_V);
379 TmpInst.setOpcode(Mips::OR_V);
395 TmpInst.setOpcode(Mips::OR_V);
411 TmpInst.setOpcode(Mips::CMPU_EQ_QB);
424 TmpInst.setOpcode(Mips::CMPU_LE_QB);
437 TmpInst.setOpcode(Mips::CMPU_LT_QB);
450 TmpInst.setOpcode(Mips::CMP_EQ_PH);
463 TmpInst.setOpcode(Mips::CMP_LE_PH);
476 TmpInst.setOpcode(Mips::CMP_LT_PH);
489 TmpInst.setOpcode(Mips::DMULT);
502 TmpInst.setOpcode(Mips::DMULTu);
515 TmpInst.setOpcode(Mips::DSDIV);
528 TmpInst.setOpcode(Mips::DUDIV);
541 TmpInst.setOpcode(Mips::JR);
551 TmpInst.setOpcode(Mips::JR64);
561 TmpInst.setOpcode(Mips::JALR64);
573 TmpInst.setOpcode(Mips::JALR);
585 TmpInst.setOpcode(Mips::JR_MM);
595 TmpInst.setOpcode(Mips::JRC16_MMR6);
605 TmpInst.setOpcode(Mips::JR_HB);
615 TmpInst.setOpcode(Mips::JR_HB64);
625 TmpInst.setOpcode(Mips::JR_HB64_R6);
635 TmpInst.setOpcode(Mips::JR_HB_R6);
645 TmpInst.setOpcode(Mips::MADD);
658 TmpInst.setOpcode(Mips::MADDU);
671 TmpInst.setOpcode(Mips::MADDU);
684 TmpInst.setOpcode(Mips::MADD);
697 TmpInst.setOpcode(Mips::MSUB);
710 TmpInst.setOpcode(Mips::MSUBU);
723 TmpInst.setOpcode(Mips::MSUBU);
736 TmpInst.setOpcode(Mips::MSUB);
749 TmpInst.setOpcode(Mips::MULT);
762 TmpInst.setOpcode(Mips::MULT);
775 TmpInst.setOpcode(Mips::MULTu);
788 TmpInst.setOpcode(Mips::MULTu);
801 TmpInst.setOpcode(Mips::PICK_PH);
817 TmpInst.setOpcode(Mips::PICK_QB);
833 TmpInst.setOpcode(Mips::SDIV);
846 TmpInst.setOpcode(Mips::UDIV);
859 TmpInst.setOpcode(Mips::SDIV_MM);
872 TmpInst.setOpcode(Mips::J);
882 TmpInst.setOpcode(Mips::JALR64);
894 TmpInst.setOpcode(Mips::JR_HB64_R6);
904 TmpInst.setOpcode(Mips::JR_HB_R6);
914 TmpInst.setOpcode(Mips::JALR);
926 TmpInst.setOpcode(Mips::JR);
936 TmpInst.setOpcode(Mips::JR64);
946 TmpInst.setOpcode(Mips::JR_HB);
956 TmpInst.setOpcode(Mips::JR_HB64);
966 TmpInst.setOpcode(Mips::JRC16_MM);
976 TmpInst.setOpcode(Mips::JRC16_MM);
986 TmpInst.setOpcode(Mips::J_MM);
996 TmpInst.setOpcode(Mips::BC_MMR6);
1006 TmpInst.setOpcode(Mips::BREAK);
1017 TmpInst.setOpcode(Mips::BREAK_MM);
1028 TmpInst.setOpcode(Mips::UDIV_MM);
1041 TmpInst.setOpcode(Mips::XOR_V);
1057 TmpInst.setOpcode(Mips::XOR_V);
1073 TmpInst.setOpcode(Mips::XOR_V);
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 2084 Inst.setOpcode(Opcode);
7138 Inst.setOpcode(it->Opcode);
gen/lib/Target/PowerPC/PPCGenDisassemblerTables.inc 6653 MI.setOpcode(Opc);
6677 TmpMI.setOpcode(Opc);
gen/lib/Target/RISCV/RISCVGenAsmMatcher.inc 953 Inst.setOpcode(Opcode);
2527 Inst.setOpcode(it->Opcode);
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 136 OutInst.setOpcode(RISCV::C_MV);
148 OutInst.setOpcode(RISCV::C_MV);
160 OutInst.setOpcode(RISCV::C_ADD);
174 OutInst.setOpcode(RISCV::C_ADD);
191 OutInst.setOpcode(RISCV::C_ADDI4SPN);
206 OutInst.setOpcode(RISCV::C_NOP);
214 OutInst.setOpcode(RISCV::C_ADDI);
228 OutInst.setOpcode(RISCV::C_LI);
240 OutInst.setOpcode(RISCV::C_ADDI16SP);
255 OutInst.setOpcode(RISCV::C_MV);
271 OutInst.setOpcode(RISCV::C_ADDIW);
286 OutInst.setOpcode(RISCV::C_LI);
302 OutInst.setOpcode(RISCV::C_ADDW);
317 OutInst.setOpcode(RISCV::C_ADDW);
334 OutInst.setOpcode(RISCV::C_AND);
348 OutInst.setOpcode(RISCV::C_AND);
365 OutInst.setOpcode(RISCV::C_ANDI);
382 OutInst.setOpcode(RISCV::C_BEQZ);
397 OutInst.setOpcode(RISCV::C_BNEZ);
409 OutInst.setOpcode(RISCV::C_EBREAK);
421 OutInst.setOpcode(RISCV::C_FLD);
436 OutInst.setOpcode(RISCV::C_FLDSP);
455 OutInst.setOpcode(RISCV::C_FLW);
471 OutInst.setOpcode(RISCV::C_FLWSP);
489 OutInst.setOpcode(RISCV::C_FSD);
504 OutInst.setOpcode(RISCV::C_FSDSP);
523 OutInst.setOpcode(RISCV::C_FSW);
539 OutInst.setOpcode(RISCV::C_FSWSP);
556 OutInst.setOpcode(RISCV::C_JAL);
565 OutInst.setOpcode(RISCV::C_J);
579 OutInst.setOpcode(RISCV::C_JR);
590 OutInst.setOpcode(RISCV::C_JALR);
604 OutInst.setOpcode(RISCV::C_LD);
619 OutInst.setOpcode(RISCV::C_LDSP);
635 OutInst.setOpcode(RISCV::C_LUI);
650 OutInst.setOpcode(RISCV::C_LW);
664 OutInst.setOpcode(RISCV::C_LWSP);
681 OutInst.setOpcode(RISCV::C_OR);
695 OutInst.setOpcode(RISCV::C_OR);
713 OutInst.setOpcode(RISCV::C_SD);
728 OutInst.setOpcode(RISCV::C_SDSP);
745 OutInst.setOpcode(RISCV::C_SLLI);
762 OutInst.setOpcode(RISCV::C_SRAI);
779 OutInst.setOpcode(RISCV::C_SRLI);
796 OutInst.setOpcode(RISCV::C_SUB);
814 OutInst.setOpcode(RISCV::C_SUBW);
831 OutInst.setOpcode(RISCV::C_SW);
845 OutInst.setOpcode(RISCV::C_SWSP);
859 OutInst.setOpcode(RISCV::C_UNIMP);
870 OutInst.setOpcode(RISCV::C_XOR);
884 OutInst.setOpcode(RISCV::C_XOR);
968 OutInst.setOpcode(RISCV::ADD);
982 OutInst.setOpcode(RISCV::ADD);
999 OutInst.setOpcode(RISCV::ADDI);
1016 OutInst.setOpcode(RISCV::ADDI);
1033 OutInst.setOpcode(RISCV::ADDI);
1051 OutInst.setOpcode(RISCV::ADDIW);
1069 OutInst.setOpcode(RISCV::ADDW);
1084 OutInst.setOpcode(RISCV::ADDW);
1101 OutInst.setOpcode(RISCV::AND);
1115 OutInst.setOpcode(RISCV::AND);
1132 OutInst.setOpcode(RISCV::ANDI);
1148 OutInst.setOpcode(RISCV::BEQ);
1164 OutInst.setOpcode(RISCV::BNE);
1178 OutInst.setOpcode(RISCV::EBREAK);
1190 OutInst.setOpcode(RISCV::FLD);
1208 OutInst.setOpcode(RISCV::FLD);
1227 OutInst.setOpcode(RISCV::FLW);
1246 OutInst.setOpcode(RISCV::FLW);
1264 OutInst.setOpcode(RISCV::FSD);
1282 OutInst.setOpcode(RISCV::FSD);
1301 OutInst.setOpcode(RISCV::FSW);
1320 OutInst.setOpcode(RISCV::FSW);
1335 OutInst.setOpcode(RISCV::JAL);
1349 OutInst.setOpcode(RISCV::JAL);
1363 OutInst.setOpcode(RISCV::JALR);
1379 OutInst.setOpcode(RISCV::JALR);
1397 OutInst.setOpcode(RISCV::LD);
1415 OutInst.setOpcode(RISCV::LD);
1431 OutInst.setOpcode(RISCV::ADDI);
1445 OutInst.setOpcode(RISCV::ADDIW);
1461 OutInst.setOpcode(RISCV::LUI);
1476 OutInst.setOpcode(RISCV::LW);
1493 OutInst.setOpcode(RISCV::LW);
1509 OutInst.setOpcode(RISCV::ADD);
1522 OutInst.setOpcode(RISCV::ADD);
1536 OutInst.setOpcode(RISCV::ADDI);
1551 OutInst.setOpcode(RISCV::ADDI);
1568 OutInst.setOpcode(RISCV::OR);
1582 OutInst.setOpcode(RISCV::OR);
1600 OutInst.setOpcode(RISCV::SD);
1618 OutInst.setOpcode(RISCV::SD);
1635 OutInst.setOpcode(RISCV::SLLI);
1652 OutInst.setOpcode(RISCV::SRAI);
1669 OutInst.setOpcode(RISCV::SRLI);
1686 OutInst.setOpcode(RISCV::SUB);
1704 OutInst.setOpcode(RISCV::SUBW);
1721 OutInst.setOpcode(RISCV::SW);
1738 OutInst.setOpcode(RISCV::SW);
1752 OutInst.setOpcode(RISCV::UNIMP);
1763 OutInst.setOpcode(RISCV::XOR);
1777 OutInst.setOpcode(RISCV::XOR);
gen/lib/Target/RISCV/RISCVGenDisassemblerTables.inc 1829 MI.setOpcode(Opc);
1853 TmpMI.setOpcode(Opc);
gen/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc 17 TmpInst.setOpcode(RISCV::JAL);
29 TmpInst.setOpcode(RISCV::JALR);
44 TmpInst.setOpcode(RISCV::JALR);
58 TmpInst.setOpcode(RISCV::JALR);
71 TmpInst.setOpcode(RISCV::JALR);
gen/lib/Target/Sparc/SparcGenAsmMatcher.inc 1572 Inst.setOpcode(Opcode);
4271 Inst.setOpcode(it->Opcode);
gen/lib/Target/Sparc/SparcGenDisassemblerTables.inc 2451 MI.setOpcode(Opc);
2475 TmpMI.setOpcode(Opc);
gen/lib/Target/SystemZ/SystemZGenAsmMatcher.inc 1345 Inst.setOpcode(Opcode);
5466 Inst.setOpcode(it->Opcode);
gen/lib/Target/SystemZ/SystemZGenDisassemblerTables.inc10824 MI.setOpcode(Opc);
10848 TmpMI.setOpcode(Opc);
gen/lib/Target/WebAssembly/WebAssemblyGenAsmMatcher.inc 162 Inst.setOpcode(Opcode);
1235 Inst.setOpcode(it->Opcode);
gen/lib/Target/X86/X86GenAsmMatcher.inc 4943 Inst.setOpcode(Opcode);
37066 Inst.setOpcode(it->Opcode);
gen/lib/Target/XCore/XCoreGenDisassemblerTables.inc 895 MI.setOpcode(Opc);
919 TmpMI.setOpcode(Opc);
include/llvm/MC/MCInstBuilder.h 27 Inst.setOpcode(Opcode);
lib/Target/AArch64/AArch64AsmPrinter.cpp 874 MOVI.setOpcode(AArch64::MOVIv2d_ns);
883 FMov.setOpcode(AArch64::FMOVWHr);
888 FMov.setOpcode(AArch64::FMOVWSr);
893 FMov.setOpcode(AArch64::FMOVXDr);
938 MovZ.setOpcode(AArch64::MOVZXi);
945 MovK.setOpcode(AArch64::MOVKXi);
959 TmpInst.setOpcode(AArch64::MOVIv16b_ns);
997 TmpInst.setOpcode(AArch64::BR);
1006 TmpInst.setOpcode(AArch64::B);
1029 Adrp.setOpcode(AArch64::ADRP);
1035 Ldr.setOpcode(AArch64::LDRXui);
1043 Add.setOpcode(AArch64::ADDXri);
1053 TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
1058 Blr.setOpcode(AArch64::BLR);
lib/Target/AArch64/AArch64InstrInfo.cpp 3494 NopInst.setOpcode(AArch64::HINT);
lib/Target/AArch64/AArch64MCInstLower.cpp 297 OutMI.setOpcode(MI->getOpcode());
308 OutMI.setOpcode(AArch64::RET);
313 OutMI.setOpcode(AArch64::RET);
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 5308 Inst.setOpcode(AArch64::TLSDESCCALL);
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 188 OutMI.setOpcode(TII->pseudoToMCOpcode(AMDGPU::S_SWAPPC_B64));
207 OutMI.setOpcode(MCOpcode);
376 OutMI.setOpcode(MI->getOpcode());
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 5847 Inst.setOpcode(NoLdsOpcode);
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 581 MI.setOpcode(NewOpcode);
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp 60 Res.setOpcode(RelaxedOpcode);
lib/Target/ARC/ARCMCInstLower.cpp 105 OutMI.setOpcode(MI->getOpcode());
lib/Target/ARM/ARMAsmPrinter.cpp 1395 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1426 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1753 TmpInst.setOpcode(Opc);
1768 TmpInst.setOpcode(ARM::LDRi12);
1781 TmpInst.setOpcode(ARM::LDRrs);
lib/Target/ARM/ARMInstrInfo.cpp 37 NopInst.setOpcode(ARM::HINT);
42 NopInst.setOpcode(ARM::MOVr);
lib/Target/ARM/ARMMCInstLower.cpp 125 OutMI.setOpcode(MI->getOpcode());
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 245 ITInst.setOpcode(ARM::t2IT);
5585 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
5586 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
5595 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
5599 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
5610 Inst.setOpcode(ARM::t2B);
5617 Inst.setOpcode(ARM::t2Bcc);
8235 TmpInst.setOpcode(Opcode);
8255 TmpInst.setOpcode(Opcode);
8273 TmpInst.setOpcode(Opcode);
8291 TmpInst.setOpcode(ARM::ADR);
8327 Inst.setOpcode(ARM::tLDRpci);
8329 Inst.setOpcode(ARM::t2LDRpci);
8332 Inst.setOpcode(ARM::t2LDRBpci);
8335 Inst.setOpcode(ARM::t2LDRHpci);
8338 Inst.setOpcode(ARM::t2LDRSBpci);
8341 Inst.setOpcode(ARM::t2LDRSHpci);
8351 TmpInst.setOpcode(ARM::LDRi12);
8353 TmpInst.setOpcode(ARM::tLDRpci);
8355 TmpInst.setOpcode(ARM::t2LDRpci);
8373 TmpInst.setOpcode(ARM::MOVi);
8377 TmpInst.setOpcode(ARM::MVNi);
8381 TmpInst.setOpcode(ARM::MOVi16);
8391 TmpInst.setOpcode(ARM::t2MOVi);
8394 TmpInst.setOpcode(ARM::t2MVNi);
8399 TmpInst.setOpcode(ARM::t2MOVi16);
8437 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8459 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8483 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8509 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8535 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8557 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8581 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8607 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8633 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8653 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8675 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8699 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8724 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8747 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8774 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8805 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8838 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8861 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8888 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8919 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8952 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8998 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9027 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9060 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9082 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9131 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9153 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9177 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9202 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9226 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9279 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9329 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9356 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9378 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9402 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9427 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9451 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9477 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9512 TmpInst.setOpcode(NewOpc);
9547 TmpInst.setOpcode(newOpc);
9600 TmpInst.setOpcode(newOpc);
9631 TmpInst.setOpcode(ARM::MOVsr);
9662 TmpInst.setOpcode(Opc);
9676 TmpInst.setOpcode(ARM::MOVsi);
9692 TmpInst.setOpcode(ARM::t2LDR_POST);
9708 TmpInst.setOpcode(ARM::t2STR_PRE);
9724 TmpInst.setOpcode(ARM::LDR_POST_IMM);
9742 TmpInst.setOpcode(ARM::STR_PRE_IMM);
9758 Inst.setOpcode(ARM::t2ADDri);
9767 Inst.setOpcode(ARM::t2SUBri);
9776 Inst.setOpcode(ARM::tADDi3);
9786 Inst.setOpcode(ARM::tSUBi3);
9804 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
9833 TmpInst.setOpcode(ARM::tADDhirr);
9846 Inst.setOpcode(ARM::t2ADDrr);
9854 Inst.setOpcode(ARM::tBcc);
9861 Inst.setOpcode(ARM::t2Bcc);
9868 Inst.setOpcode(ARM::t2B);
9875 Inst.setOpcode(ARM::tB);
9894 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
9913 Inst.setOpcode(ARM::t2STMIA_UPD);
9926 Inst.setOpcode(ARM::t2LDMIA_UPD);
9937 Inst.setOpcode(ARM::t2STMDB_UPD);
9953 TmpInst.setOpcode(ARM::tMOVi8);
9974 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
10004 TmpInst.setOpcode(NewOpc);
10022 TmpInst.setOpcode(ARM::MOVr);
10056 TmpInst.setOpcode(newOpc);
10100 TmpInst.setOpcode(NewOpc);
10134 TmpInst.setOpcode(NewOpc);
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 2217 Inst.setOpcode(ARM::RFEDA);
2220 Inst.setOpcode(ARM::RFEDA_UPD);
2223 Inst.setOpcode(ARM::RFEDB);
2226 Inst.setOpcode(ARM::RFEDB_UPD);
2229 Inst.setOpcode(ARM::RFEIA);
2232 Inst.setOpcode(ARM::RFEIA_UPD);
2235 Inst.setOpcode(ARM::RFEIB);
2238 Inst.setOpcode(ARM::RFEIB_UPD);
2241 Inst.setOpcode(ARM::SRSDA);
2244 Inst.setOpcode(ARM::SRSDA_UPD);
2247 Inst.setOpcode(ARM::SRSDB);
2250 Inst.setOpcode(ARM::SRSDB_UPD);
2253 Inst.setOpcode(ARM::SRSIA);
2256 Inst.setOpcode(ARM::SRSIA_UPD);
2259 Inst.setOpcode(ARM::SRSIB);
2262 Inst.setOpcode(ARM::SRSIB_UPD);
2342 Inst.setOpcode(ARM::CPS3p);
2347 Inst.setOpcode(ARM::CPS2p);
2352 Inst.setOpcode(ARM::CPS1p);
2357 Inst.setOpcode(ARM::CPS1p);
2382 Inst.setOpcode(ARM::t2CPS3p);
2387 Inst.setOpcode(ARM::t2CPS2p);
2392 Inst.setOpcode(ARM::t2CPS1p);
2400 Inst.setOpcode(ARM::t2HINT);
2529 Inst.setOpcode(ARM::SETPAN);
2636 Inst.setOpcode(ARM::BLXi);
3768 Inst.setOpcode(ARM::t2LDRBpci);
3771 Inst.setOpcode(ARM::t2LDRHpci);
3774 Inst.setOpcode(ARM::t2LDRSHpci);
3777 Inst.setOpcode(ARM::t2LDRSBpci);
3780 Inst.setOpcode(ARM::t2LDRpci);
3783 Inst.setOpcode(ARM::t2PLDpci);
3786 Inst.setOpcode(ARM::t2PLIpci);
3800 Inst.setOpcode(ARM::t2PLDWs);
3803 Inst.setOpcode(ARM::t2PLIs);
3856 Inst.setOpcode(ARM::t2LDRpci);
3859 Inst.setOpcode(ARM::t2LDRBpci);
3862 Inst.setOpcode(ARM::t2LDRSBpci);
3865 Inst.setOpcode(ARM::t2LDRHpci);
3868 Inst.setOpcode(ARM::t2LDRSHpci);
3871 Inst.setOpcode(ARM::t2PLDpci);
3874 Inst.setOpcode(ARM::t2PLIpci);
3888 Inst.setOpcode(ARM::t2PLDWi8);
3891 Inst.setOpcode(ARM::t2PLIi8);
3937 Inst.setOpcode(ARM::t2LDRpci);
3940 Inst.setOpcode(ARM::t2LDRHpci);
3943 Inst.setOpcode(ARM::t2LDRSHpci);
3946 Inst.setOpcode(ARM::t2LDRBpci);
3949 Inst.setOpcode(ARM::t2LDRSBpci);
3952 Inst.setOpcode(ARM::t2PLDpci);
3955 Inst.setOpcode(ARM::t2PLIpci);
3968 Inst.setOpcode(ARM::t2PLDWi12);
3971 Inst.setOpcode(ARM::t2PLIi12);
4011 Inst.setOpcode(ARM::t2LDRpci);
4014 Inst.setOpcode(ARM::t2LDRBpci);
4017 Inst.setOpcode(ARM::t2LDRHpci);
4020 Inst.setOpcode(ARM::t2LDRSBpci);
4023 Inst.setOpcode(ARM::t2LDRSHpci);
4055 Inst.setOpcode(ARM::t2PLDpci);
4058 Inst.setOpcode(ARM::t2PLIpci);
4290 Inst.setOpcode(ARM::t2LDRpci);
4294 Inst.setOpcode(ARM::t2LDRBpci);
4298 Inst.setOpcode(ARM::t2LDRHpci);
4303 Inst.setOpcode(ARM::t2PLIpci);
4305 Inst.setOpcode(ARM::t2LDRSBpci);
4309 Inst.setOpcode(ARM::t2LDRSHpci);
4526 Inst.setOpcode(ARM::t2DSB);
4529 Inst.setOpcode(ARM::t2DMB);
4532 Inst.setOpcode(ARM::t2ISB);
5659 Inst.setOpcode(ARM::VMOVv2f32);
5664 Inst.setOpcode(ARM::VMOVv1i64);
5666 Inst.setOpcode(ARM::VMOVv8i8);
5671 Inst.setOpcode(ARM::VMVNv2i32);
5673 Inst.setOpcode(ARM::VMOVv2i32);
5678 Inst.setOpcode(ARM::VMVNv2i32);
5680 Inst.setOpcode(ARM::VMOVv2i32);
5718 Inst.setOpcode(ARM::VMOVv4f32);
5723 Inst.setOpcode(ARM::VMOVv2i64);
5725 Inst.setOpcode(ARM::VMOVv16i8);
5730 Inst.setOpcode(ARM::VMVNv4i32);
5732 Inst.setOpcode(ARM::VMOVv4i32);
5737 Inst.setOpcode(ARM::VMVNv4i32);
5739 Inst.setOpcode(ARM::VMOVv4i32);
6003 Inst.setOpcode(ARM::MVE_LCTP);
6464 Inst.setOpcode(ARM::MVE_SQRSHR);
6468 Inst.setOpcode(ARM::MVE_UQRSHL);
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 337 Res.setOpcode(RelaxedOp);
347 Res.setOpcode(RelaxedOp);
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 267 NewMI.setOpcode(Opcode);
lib/Target/ARM/Thumb1InstrInfo.cpp 27 NopInst.setOpcode(ARM::tMOVr);
lib/Target/ARM/Thumb2InstrInfo.cpp 46 NopInst.setOpcode(ARM::tHINT);
lib/Target/AVR/AVRMCInstLower.cpp 63 OutMI.setOpcode(MI.getOpcode());
lib/Target/BPF/BPFMCInstLower.cpp 48 OutMI.setOpcode(MI->getOpcode());
lib/Target/BPF/BTFDebug.cpp 1132 OutMI.setOpcode(BPF::MOV_ri);
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp 163 MCB.setOpcode(Hexagon::BUNDLE);
533 NewInst.setOpcode(MCI.getOpcode());
1226 TmpInst.setOpcode(opCode);
1314 Inst.setOpcode(Hexagon::A2_addi);
1348 Inst.setOpcode(Hexagon::C2_cmpgti);
1362 TmpInst.setOpcode(Hexagon::C2_cmpeq);
1372 Inst.setOpcode(Hexagon::C2_cmpgtui);
1388 Inst.setOpcode(Hexagon::A2_combinew);
1403 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1419 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1434 Inst.setOpcode(Hexagon::V6_vcombine);
1532 TmpInst.setOpcode(Hexagon::L2_loadrigp);
1534 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1612 Inst.setOpcode(Hexagon::S2_tableidxb);
1625 TmpInst.setOpcode(Hexagon::S2_tableidxh);
1645 TmpInst.setOpcode(Hexagon::S2_tableidxw);
1665 TmpInst.setOpcode(Hexagon::S2_tableidxd);
1676 Inst.setOpcode(Hexagon::M2_mpyi);
1694 TmpInst.setOpcode(Hexagon::M2_mpysin);
1696 TmpInst.setOpcode(Hexagon::M2_mpysip);
1712 TmpInst.setOpcode(Hexagon::A2_tfr);
1722 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1750 TmpInst.setOpcode(Hexagon::A2_combinew);
1760 Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1769 Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1774 Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1786 Inst.setOpcode(Hexagon::A2_addsph);
1791 Inst.setOpcode(Hexagon::A2_addspl);
1803 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
1808 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
1823 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
1828 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
1846 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
1851 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
1866 Inst.setOpcode(Hexagon::S2_vsathub);
1872 Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
1894 TmpInst.setOpcode(Hexagon::A2_combinew);
1904 Inst.setOpcode(Hexagon::S5_vasrhrnd);
1913 TmpInst.setOpcode(Hexagon::A2_subri);
1923 Inst.setOpcode(Hexagon::L2_loadrubgp);
1927 Inst.setOpcode(Hexagon::L2_loadrbgp);
1931 Inst.setOpcode(Hexagon::L2_loadruhgp);
1935 Inst.setOpcode(Hexagon::L2_loadrhgp);
1939 Inst.setOpcode(Hexagon::L2_loadrigp);
1943 Inst.setOpcode(Hexagon::L2_loadrdgp);
1947 Inst.setOpcode(Hexagon::S2_storerbgp);
1951 Inst.setOpcode(Hexagon::S2_storerhgp);
1955 Inst.setOpcode(Hexagon::S2_storerfgp);
1959 Inst.setOpcode(Hexagon::S2_storerigp);
1963 Inst.setOpcode(Hexagon::S2_storerdgp);
1967 Inst.setOpcode(Hexagon::S2_storerbnewgp);
1971 Inst.setOpcode(Hexagon::S2_storerhnewgp);
1975 Inst.setOpcode(Hexagon::S2_storerinewgp);
1978 Inst.setOpcode(Hexagon::A2_andir);
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp 176 MI.setOpcode(Hexagon::BUNDLE);
205 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
213 MI.setOpcode(L6_deallocframe_map_to_raw);
221 MI.setOpcode(L6_return_map_to_raw);
229 MI.setOpcode(L4_return_map_to_raw_t);
237 MI.setOpcode(L4_return_map_to_raw_f);
245 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
253 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
261 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
269 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
384 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
lib/Target/Hexagon/HexagonAsmPrinter.cpp 249 T.setOpcode(Inst.getOpcode());
278 Inst.setOpcode(Hexagon::A2_addi);
292 Inst.setOpcode(Hexagon::A2_paddif);
299 Inst.setOpcode(Hexagon::A2_paddit);
306 Inst.setOpcode(Hexagon::A2_paddifnew);
313 Inst.setOpcode(Hexagon::A2_padditnew);
320 Inst.setOpcode(Hexagon::A2_andir);
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
352 TmpInst.setOpcode(Hexagon::L2_loadrigp);
365 MappedInst.setOpcode(Hexagon::C2_or);
378 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
380 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
389 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
391 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
401 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
403 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
413 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
415 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
421 Inst.setOpcode(Hexagon::J2_call);
433 TmpInst.setOpcode(Hexagon::S2_vsathub);
439 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
460 TmpInst.setOpcode(Hexagon::A2_combinew);
473 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
475 TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
496 TmpInst.setOpcode(Hexagon::A2_tfr);
502 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
519 TmpInst.setOpcode(Hexagon::A2_combineii);
545 MappedInst.setOpcode(Hexagon::A2_combinew);
557 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
571 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
585 MappedInst.setOpcode(Hexagon::M2_mpysin);
589 MappedInst.setOpcode(Hexagon::M2_mpysip);
598 MappedInst.setOpcode(Hexagon::A2_addsph);
600 MappedInst.setOpcode(Hexagon::A2_addspl);
610 TmpInst.setOpcode(Hexagon::V6_vxor);
623 TmpInst.setOpcode(Hexagon::V6_vsubw_dv);
745 MCB.setOpcode(Hexagon::BUNDLE);
lib/Target/Hexagon/HexagonMCInstLower.cpp 108 MCI->setOpcode(MI->getOpcode());
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp 656 Res.setOpcode(Hexagon::BUNDLE);
733 Nop->setOpcode(Hexagon::A2_nop);
lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp 213 CompoundInsn->setOpcode(compoundOpcode);
226 CompoundInsn->setOpcode(compoundOpcode);
240 CompoundInsn->setOpcode(compoundOpcode);
253 CompoundInsn->setOpcode(compoundOpcode);
266 CompoundInsn->setOpcode(compoundOpcode);
284 CompoundInsn->setOpcode(compoundOpcode);
302 CompoundInsn->setOpcode(compoundOpcode);
313 CompoundInsn->setOpcode(compoundOpcode);
324 CompoundInsn->setOpcode(compoundOpcode);
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 715 Result.setOpcode(Hexagon::SA1_inc);
721 Result.setOpcode(Hexagon::SA1_dec);
728 Result.setOpcode(Hexagon::SA1_addsp);
734 Result.setOpcode(Hexagon::SA1_addi);
740 Result.setOpcode(Hexagon::SA1_addrx);
746 Result.setOpcode(Hexagon::SS2_allocframe);
751 Result.setOpcode(Hexagon::SA1_zxtb);
756 Result.setOpcode(Hexagon::SA1_and1);
762 Result.setOpcode(Hexagon::SA1_cmpeqi);
771 Result.setOpcode(Hexagon::SA1_combine1i);
777 Result.setOpcode(Hexagon::SA1_combine3i);
783 Result.setOpcode(Hexagon::SA1_combine0i);
789 Result.setOpcode(Hexagon::SA1_combine2i);
796 Result.setOpcode(Hexagon::SA1_combinezr);
801 Result.setOpcode(Hexagon::SA1_combinerz);
807 Result.setOpcode(Hexagon::SL2_return_tnew);
811 Result.setOpcode(Hexagon::SL2_return_fnew);
814 Result.setOpcode(Hexagon::SL2_return_f);
817 Result.setOpcode(Hexagon::SL2_return_t);
820 Result.setOpcode(Hexagon::SL2_return);
823 Result.setOpcode(Hexagon::SL2_deallocframe);
828 Result.setOpcode(Hexagon::SL2_jumpr31);
832 Result.setOpcode(Hexagon::SL2_jumpr31_f);
838 Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
842 Result.setOpcode(Hexagon::SL2_jumpr31_t);
848 Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
851 Result.setOpcode(Hexagon::SL2_loadrb_io);
857 Result.setOpcode(Hexagon::SL2_loadrd_sp);
862 Result.setOpcode(Hexagon::SL2_loadrh_io);
868 Result.setOpcode(Hexagon::SL1_loadrub_io);
874 Result.setOpcode(Hexagon::SL2_loadruh_io);
881 Result.setOpcode(Hexagon::SL2_loadri_sp);
886 Result.setOpcode(Hexagon::SL1_loadri_io);
896 Result.setOpcode(Hexagon::SS2_storebi0);
901 Result.setOpcode(Hexagon::SS2_storebi1);
908 Result.setOpcode(Hexagon::SS1_storeb_io);
914 Result.setOpcode(Hexagon::SS2_stored_sp);
919 Result.setOpcode(Hexagon::SS2_storeh_io);
928 Result.setOpcode(Hexagon::SS2_storewi0);
933 Result.setOpcode(Hexagon::SS2_storewi1);
938 Result.setOpcode(Hexagon::SS2_storew_sp);
946 Result.setOpcode(Hexagon::SS2_storew_sp);
950 Result.setOpcode(Hexagon::SS1_storew_io);
957 Result.setOpcode(Hexagon::SA1_sxtb);
962 Result.setOpcode(Hexagon::SA1_sxth);
967 Result.setOpcode(Hexagon::SA1_tfr);
972 Result.setOpcode(Hexagon::SA1_clrfnew);
977 Result.setOpcode(Hexagon::SA1_clrtnew);
982 Result.setOpcode(Hexagon::SA1_clrf);
987 Result.setOpcode(Hexagon::SA1_clrt);
994 Result.setOpcode(Hexagon::SA1_setin1);
999 Result.setOpcode(Hexagon::SA1_seti);
1005 Result.setOpcode(Hexagon::SA1_zxtb);
1011 Result.setOpcode(Hexagon::SA1_zxth);
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp 166 XMI.setOpcode(Hexagon::A4_ext);
181 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
807 Nop.setOpcode(Hexagon::A2_nop);
lib/Target/Lanai/LanaiAsmPrinter.cpp 177 TmpInst.setOpcode(Lanai::BT);
lib/Target/Lanai/LanaiMCInstLower.cpp 94 OutMI.setOpcode(MI->getOpcode());
lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp 357 MI.setOpcode(MSP430::JMP);
359 MI.setOpcode(MSP430::JCC);
lib/Target/MSP430/MSP430MCInstLower.cpp 116 OutMI.setOpcode(MI->getOpcode());
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1933 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
2010 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ);
2042 JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM);
2044 JalrInst.setOpcode(Mips::JALR);
2464 Inst.setOpcode(Mips::SLTi64);
2470 Inst.setOpcode(Mips::SLTiu64);
2565 JalrInst.setOpcode(Mips::JALRS16_MM);
2568 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM);
2571 JalrInst.setOpcode(Mips::JALR);
2578 JalrInst.setOpcode(Mips::JALRS_MM);
2580 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
3496 Inst.setOpcode(Mips::BEQ_MM);
3506 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
3513 Inst.setOpcode(Mips::BEQ_MM);
3739 Inst.setOpcode(NewOpcode);
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 680 MI.setOpcode(Mips::BOVC);
683 MI.setOpcode(Mips::BEQC);
686 MI.setOpcode(Mips::BEQZALC);
708 MI.setOpcode(Mips::BOVC_MMR6);
715 MI.setOpcode(Mips::BEQC_MMR6);
722 MI.setOpcode(Mips::BEQZALC_MMR6);
753 MI.setOpcode(Mips::BNVC);
756 MI.setOpcode(Mips::BNEC);
759 MI.setOpcode(Mips::BNEZALC);
781 MI.setOpcode(Mips::BNVC_MMR6);
788 MI.setOpcode(Mips::BNEC_MMR6);
795 MI.setOpcode(Mips::BNEZALC_MMR6);
825 MI.setOpcode(Mips::BGTZC_MMR6);
827 MI.setOpcode(Mips::BLTZC_MMR6);
829 MI.setOpcode(Mips::BLTC_MMR6);
864 MI.setOpcode(Mips::BLEZC_MMR6);
866 MI.setOpcode(Mips::BGEZC_MMR6);
869 MI.setOpcode(Mips::BGEC_MMR6);
907 MI.setOpcode(Mips::BLEZC);
909 MI.setOpcode(Mips::BGEZC);
912 MI.setOpcode(Mips::BGEC);
951 MI.setOpcode(Mips::BGTZC);
953 MI.setOpcode(Mips::BLTZC);
955 MI.setOpcode(Mips::BLTC);
993 MI.setOpcode(Mips::BGTZ);
996 MI.setOpcode(Mips::BGTZALC);
999 MI.setOpcode(Mips::BLTZALC);
1002 MI.setOpcode(Mips::BLTUC);
1043 MI.setOpcode(Mips::BLEZALC);
1045 MI.setOpcode(Mips::BGEZALC);
1048 MI.setOpcode(Mips::BGEUC);
1089 MI.setOpcode(Mips::DEXT);
1134 MI.setOpcode(Mips::DINS);
2557 MI.setOpcode(Mips::BGTZALC_MMR6);
2562 MI.setOpcode(Mips::BLTZALC_MMR6);
2567 MI.setOpcode(Mips::BLTUC_MMR6);
2605 MI.setOpcode(Mips::BLEZALC_MMR6);
2609 MI.setOpcode(Mips::BGEZALC_MMR6);
2614 MI.setOpcode(Mips::BGEUC_MMR6);
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 77 Inst.setOpcode(Mips::DSLL32);
80 Inst.setOpcode(Mips::DSRL32);
83 Inst.setOpcode(Mips::DSRA32);
86 Inst.setOpcode(Mips::DROTR32);
211 TmpInst.setOpcode (NewOpcode);
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp 104 MaskInst.setOpcode(Mips::AND);
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 174 TmpInst.setOpcode(Opcode);
183 TmpInst.setOpcode(Opcode);
203 TmpInst.setOpcode(Opcode);
214 TmpInst.setOpcode(Opcode);
232 TmpInst.setOpcode(Opcode);
252 TmpInst.setOpcode(Opcode);
1169 TmpInst.setOpcode(Mips::LUi);
1181 TmpInst.setOpcode(Mips::ADDiu);
1194 TmpInst.setOpcode(Mips::ADDu);
1297 Inst.setOpcode(Mips::OR);
1302 Inst.setOpcode(Mips::LD);
lib/Target/Mips/MipsAsmPrinter.cpp 123 TmpInst0.setOpcode(Mips::JALR64);
128 TmpInst0.setOpcode(Mips::JRC16_MMR6);
130 TmpInst0.setOpcode(Mips::JALR);
135 TmpInst0.setOpcode(Mips::JR_MM);
138 TmpInst0.setOpcode(Mips::JR);
854 I.setOpcode(Mips::JAL);
863 I.setOpcode(Opcode);
882 I.setOpcode(Opcode);
892 I.setOpcode(Opcode);
lib/Target/Mips/MipsMCInstLower.cpp 218 OutMI.setOpcode(Mips::LUi);
256 OutMI.setOpcode(Opcode);
321 OutMI.setOpcode(MI->getOpcode());
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 213 OutMI.setOpcode(MI->getOpcode());
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 721 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
733 TmpInst.setOpcode(PPC::DCBT);
743 TmpInst.setOpcode(PPC::DCBTST);
760 TmpInst.setOpcode(PPC::DCBF);
769 TmpInst.setOpcode(PPC::LA);
778 TmpInst.setOpcode(PPC::ADDI);
787 TmpInst.setOpcode(PPC::ADDIS);
796 TmpInst.setOpcode(PPC::ADDIC);
805 TmpInst.setOpcode(PPC::ADDICo);
817 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
831 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
845 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
860 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
874 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
887 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
900 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
913 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
927 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
941 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
954 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
967 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
980 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
992 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1003 TmpInst.setOpcode(PPC::ADDPCIS);
1013 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1025 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1038 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1054 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1071 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1089 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1101 Inst.setOpcode(PPC::MFSPR);
1108 TmpInst.setOpcode(PPC::CP_COPY);
1119 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
lib/Target/PowerPC/PPCAsmPrinter.cpp 652 TmpInst.setOpcode(PPC::LWZ);
669 TmpInst.setOpcode(PPC::ADD4);
684 TmpInst.setOpcode(PPC::LWZ);
742 TmpInst.setOpcode(PPC::LD);
771 TmpInst.setOpcode(PPC::ADDIS);
801 TmpInst.setOpcode(PPC::LWZ);
832 TmpInst.setOpcode(PPC::ADDIS8);
872 TmpInst.setOpcode(PPC::LD);
904 TmpInst.setOpcode(PPC::ADDI8);
942 TmpInst.setOpcode(IsPPC64 ? PPC::LD : PPC::LWZ);
1227 RetInst.setOpcode(RetOpcode);
1277 RetInst.setOpcode(PPC::BLR8);
lib/Target/PowerPC/PPCInstrInfo.cpp 489 NopInst.setOpcode(PPC::NOP);
lib/Target/PowerPC/PPCMCInstLower.cpp 152 OutMI.setOpcode(MI->getOpcode());
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp 116 Res.setOpcode(RISCV::BEQ);
123 Res.setOpcode(RISCV::BNE);
130 Res.setOpcode(RISCV::JAL);
136 Res.setOpcode(RISCV::JAL);
lib/Target/RISCV/RISCVMCInstLower.cpp 130 OutMI.setOpcode(MI->getOpcode());
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 546 TmpInst.setOpcode(SP::SETHIi);
571 TmpInst.setOpcode(SP::ORri);
lib/Target/Sparc/SparcAsmPrinter.cpp 109 CallInst.setOpcode(SP::CALL);
119 SETHIInst.setOpcode(SP::SETHIi);
130 Inst.setOpcode(Opcode);
lib/Target/Sparc/SparcMCInstLower.cpp 98 OutMI.setOpcode(MI->getOpcode());
lib/Target/SystemZ/SystemZAsmPrinter.cpp 100 LoweredMI.setOpcode(Opcode);
lib/Target/SystemZ/SystemZMCInstLower.cpp 95 OutMI.setOpcode(MI->getOpcode());
lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp 191 MI.setOpcode(WasmInst->Opcode);
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 208 OutMI.setOpcode(MI->getOpcode());
332 OutMI.setOpcode(StackOpcode);
lib/Target/X86/AsmParser/X86AsmParser.cpp 2915 Inst.setOpcode(NewOpc);
2933 Inst.setOpcode(NewOpc);
3074 Inst.setOpcode(X86::WAIT);
lib/Target/X86/Disassembler/X86Disassembler.cpp 816 mcInst.setOpcode(insn.instructionID);
822 mcInst.setOpcode(X86::XRELEASE_PREFIX);
824 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp 311 Res.setOpcode(RelaxedOp);
lib/Target/X86/X86InstrInfo.cpp 6912 NopInst.setOpcode(X86::NOOP);
lib/Target/X86/X86MCInstLower.cpp 309 Inst.setOpcode(Opcode);
337 Inst.setOpcode(NewOpcode);
388 Inst.setOpcode(Opcode);
466 OutMI.setOpcode(MI->getOpcode());
519 OutMI.setOpcode(NewOpc);
533 OutMI.setOpcode(NewOpc);
634 OutMI.setOpcode(NewOpc);
705 OutMI.setOpcode(NewOpc);
725 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
732 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
741 OutMI.setOpcode(getRetOpcode(Subtarget));
754 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
760 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
768 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
785 OutMI.setOpcode(Opcode);
1144 CallInst.setOpcode(CallOpcode);
1170 MI.setOpcode(Opcode);
1206 MCI.setOpcode(Opcode);
1223 MCI.setOpcode(X86::PUSH64rmr);
1545 Ret.setOpcode(OpCode);
1578 TC.setOpcode(OpCode);
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp 281 Inst.setOpcode(XCore::STW_2rus);
284 Inst.setOpcode(XCore::LDW_2rus);
287 Inst.setOpcode(XCore::ADD_3r);
290 Inst.setOpcode(XCore::SUB_3r);
293 Inst.setOpcode(XCore::SHL_3r);
296 Inst.setOpcode(XCore::SHR_3r);
299 Inst.setOpcode(XCore::EQ_3r);
302 Inst.setOpcode(XCore::AND_3r);
305 Inst.setOpcode(XCore::OR_3r);
308 Inst.setOpcode(XCore::LDW_3r);
311 Inst.setOpcode(XCore::LD16S_3r);
314 Inst.setOpcode(XCore::LD8U_3r);
317 Inst.setOpcode(XCore::ADD_2rus);
320 Inst.setOpcode(XCore::SUB_2rus);
323 Inst.setOpcode(XCore::SHL_2rus);
326 Inst.setOpcode(XCore::SHR_2rus);
329 Inst.setOpcode(XCore::EQ_2rus);
332 Inst.setOpcode(XCore::TSETR_3r);
335 Inst.setOpcode(XCore::LSS_3r);
338 Inst.setOpcode(XCore::LSU_3r);
445 Inst.setOpcode(XCore::STW_l3r);
448 Inst.setOpcode(XCore::XOR_l3r);
451 Inst.setOpcode(XCore::ASHR_l3r);
454 Inst.setOpcode(XCore::LDAWF_l3r);
457 Inst.setOpcode(XCore::LDAWB_l3r);
460 Inst.setOpcode(XCore::LDA16F_l3r);
463 Inst.setOpcode(XCore::LDA16B_l3r);
466 Inst.setOpcode(XCore::MUL_l3r);
469 Inst.setOpcode(XCore::DIVS_l3r);
472 Inst.setOpcode(XCore::DIVU_l3r);
475 Inst.setOpcode(XCore::ST16_l3r);
478 Inst.setOpcode(XCore::ST8_l3r);
481 Inst.setOpcode(XCore::ASHR_l2rus);
484 Inst.setOpcode(XCore::OUTPW_l2rus);
487 Inst.setOpcode(XCore::INPW_l2rus);
490 Inst.setOpcode(XCore::LDAWF_l2rus);
493 Inst.setOpcode(XCore::LDAWB_l2rus);
496 Inst.setOpcode(XCore::CRC_l3r);
499 Inst.setOpcode(XCore::REMS_l3r);
502 Inst.setOpcode(XCore::REMU_l3r);
673 Inst.setOpcode(XCore::LMUL_l6r);
lib/Target/XCore/XCoreMCInstLower.cpp 104 OutMI.setOpcode(MI->getOpcode());
tools/llvm-exegesis/lib/BenchmarkResult.cpp 79 Value.setOpcode(getInstrOpcode(Piece));
tools/llvm-exegesis/lib/CodeTemplate.cpp 59 Result.setOpcode(Instr.Description->Opcode);