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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 9647 { 2800, 2, 1, 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #2800 = MOVi32imm
9648 { 2801, 2, 1, 0, 671, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2801 = MOVi64imm
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc18009 { 1947, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm), 0x5ULL, ImplicitList1, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1947 = S_CMOV_B32
18010 { 1948, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm), 0x5ULL, ImplicitList1, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1948 = S_CMOV_B64
18069 { 2007, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x21ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #2007 = S_MOVK_I32
18075 { 2013, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x5ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2013 = S_MOV_B32
18077 { 2015, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x5ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2015 = S_MOV_B64
18380 { 2318, 2, 1, 8, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x40000000000402ULL, ImplicitList2, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2318 = V_ACCVGPR_WRITE_B32
19927 { 3865, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #3865 = V_MOV_B32_dpp
19928 { 3866, 2, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x82ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3866 = V_MOV_B32_e32
19929 { 3867, 2, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x402ULL, ImplicitList2, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #3867 = V_MOV_B32_e64
19931 { 3869, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #3869 = V_MOV_B32_sdwa
gen/lib/Target/ARC/ARCGenInstrInfo.inc 1046 { 403, 2, 1, 4, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #403 = MOV_rs12
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6059 { 226, 5, 1, 4, 866, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #226 = MOVCCi
6060 { 227, 5, 1, 4, 864, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #227 = MOVCCi16
6061 { 228, 5, 1, 8, 330, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #228 = MOVCCi32imm
6070 { 237, 2, 1, 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #237 = MOVi32imm
6086 { 253, 5, 1, 4, 866, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #253 = MVNCCi
6368 { 535, 5, 1, 4, 678, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #535 = t2MOVCCi
6369 { 536, 5, 1, 4, 678, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #536 = t2MOVCCi16
6370 { 537, 5, 1, 8, 353, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #537 = t2MOVCCi32imm
6380 { 547, 2, 1, 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #547 = t2MOVi32imm
6383 { 550, 5, 1, 4, 693, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #550 = t2MVNCCi
6586 { 753, 5, 1, 4, 864, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #753 = MOVi
6587 { 754, 4, 1, 4, 864, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #754 = MOVi16
7458 { 1625, 5, 1, 4, 708, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1625 = MVNi
9720 { 3887, 5, 1, 4, 679, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr }, // Inst #3887 = t2MOVi
9721 { 3888, 4, 1, 4, 679, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo454, -1 ,nullptr }, // Inst #3888 = t2MOVi16
9737 { 3904, 5, 1, 4, 694, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr }, // Inst #3904 = t2MVNi
10010 { 4177, 5, 2, 2, 1017, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo515, -1 ,nullptr }, // Inst #4177 = tMOVi8
gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc 3813 { 183, 2, 1, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #183 = A2_tfrpi
3921 { 291, 3, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x214800029ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #291 = PS_fi
3922 { 292, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x216800029ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #292 = PS_fia
4398 { 768, 3, 1, 4, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x112800000ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #768 = A2_combineii
4479 { 849, 2, 1, 4, 3, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x212808000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #849 = A2_tfrsi
4642 { 1012, 3, 1, 4, 6, 0|(1ULL<<MCID::MoveImm), 0x194808c00ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1012 = C2_cmoveif
4643 { 1013, 3, 1, 4, 6, 0|(1ULL<<MCID::MoveImm), 0x194808400ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1013 = C2_cmoveit
4644 { 1014, 3, 1, 4, 7, 0|(1ULL<<MCID::MoveImm), 0x194809c00ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1014 = C2_cmovenewif
4645 { 1015, 3, 1, 4, 7, 0|(1ULL<<MCID::MoveImm), 0x194809400ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1015 = C2_cmovenewit
4689 { 1059, 2, 1, 4, 29, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x25ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #1059 = CONST32
4690 { 1060, 2, 1, 4, 29, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x25ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1060 = CONST64
4769 { 1139, 2, 1, 4, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #1139 = HI
5177 { 1547, 2, 1, 4, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x8000ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #1547 = LO
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc 3945 { 1037, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1037 = LI
3946 { 1038, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1038 = LI8
3947 { 1039, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1039 = LIS
3948 { 1040, 2, 1, 4, 116, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1040 = LIS8
4853 { 1945, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1945 = V_SET0
4854 { 1946, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1946 = V_SET0B
4855 { 1947, 1, 1, 4, 98, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1947 = V_SET0H
4856 { 1948, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1948 = V_SETALLONES
4857 { 1949, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1949 = V_SETALLONESB
4858 { 1950, 1, 1, 4, 162, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x28ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1950 = V_SETALLONESH
5093 { 2185, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2185 = XXLEQVOnes
5100 { 2192, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2192 = XXLXORdpz
5101 { 2193, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2193 = XXLXORspz
5102 { 2194, 1, 1, 4, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2194 = XXLXORz
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4629 { 309, 2, 1, 0, 96, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #309 = IIFMux
4642 { 322, 2, 1, 0, 40, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #322 = LHIMux
5547 { 1227, 2, 1, 6, 97, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1227 = IIHF
5550 { 1230, 2, 1, 6, 100, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1230 = IILF
5659 { 1339, 2, 1, 6, 86, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1339 = LARL
5718 { 1398, 2, 1, 6, 39, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1398 = LGFI
5723 { 1403, 2, 1, 4, 39, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1403 = LGHI
5731 { 1411, 2, 1, 4, 40, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1411 = LHI
5755 { 1435, 2, 1, 6, 37, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1435 = LLIHF
5756 { 1436, 2, 1, 4, 37, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1436 = LLIHH
5757 { 1437, 2, 1, 4, 37, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1437 = LLIHL
5758 { 1438, 2, 1, 6, 38, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1438 = LLILF
5759 { 1439, 2, 1, 4, 38, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1439 = LLILH
5760 { 1440, 2, 1, 4, 38, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1440 = LLILL
6038 { 1718, 1, 1, 4, 340, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1718 = LZDR
6039 { 1719, 1, 1, 4, 340, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1719 = LZER
6042 { 1722, 1, 1, 4, 341, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1722 = LZXR
6857 { 2537, 2, 1, 6, 525, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2537 = VGBM
6870 { 2550, 4, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo348, -1 ,nullptr }, // Inst #2550 = VGM
6871 { 2551, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2551 = VGMB
6872 { 2552, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2552 = VGMF
6873 { 2553, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2553 = VGMG
6874 { 2554, 3, 1, 6, 526, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2554 = VGMH
7054 { 2734, 1, 1, 6, 524, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2734 = VONE
7087 { 2767, 3, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2767 = VREPI
7088 { 2768, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2768 = VREPIB
7089 { 2769, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2769 = VREPIF
7090 { 2770, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2770 = VREPIG
7091 { 2771, 2, 1, 6, 527, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2771 = VREPIH
7200 { 2880, 1, 1, 6, 523, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2880 = VZERO
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 2053 { 498, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo89, -1 ,nullptr }, // Inst #498 = CONST_F32
2054 { 499, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr }, // Inst #499 = CONST_F32_S
2055 { 500, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #500 = CONST_F64
2056 { 501, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr }, // Inst #501 = CONST_F64_S
2057 { 502, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr }, // Inst #502 = CONST_I32
2058 { 503, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #503 = CONST_I32_S
2059 { 504, 2, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr }, // Inst #504 = CONST_I64
2060 { 505, 1, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #505 = CONST_I64_S
2061 { 506, 17, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr }, // Inst #506 = CONST_V128_v16i8
2062 { 507, 16, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr }, // Inst #507 = CONST_V128_v16i8_S
2063 { 508, 3, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr }, // Inst #508 = CONST_V128_v2f64
2064 { 509, 2, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr }, // Inst #509 = CONST_V128_v2f64_S
2065 { 510, 3, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr }, // Inst #510 = CONST_V128_v2i64
2066 { 511, 2, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr }, // Inst #511 = CONST_V128_v2i64_S
2067 { 512, 5, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr }, // Inst #512 = CONST_V128_v4f32
2068 { 513, 4, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr }, // Inst #513 = CONST_V128_v4f32_S
2069 { 514, 5, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr }, // Inst #514 = CONST_V128_v4i32
2070 { 515, 4, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #515 = CONST_V128_v4i32_S
2071 { 516, 9, 1, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #516 = CONST_V128_v8i16
2072 { 517, 8, 0, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #517 = CONST_V128_v8i16_S
gen/lib/Target/X86/X86GenInstrInfo.inc17900 { 212, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr }, // Inst #212 = MOV32r0
17937 { 249, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #249 = XOR32_FP
17938 { 250, 2, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #250 = XOR64_FP
19340 { 1652, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2e00080082ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1652 = MOV16ri
19360 { 1672, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2e000c0102ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #1672 = MOV32ri
19377 { 1689, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x2e00130002ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1689 = MOV64ri
19378 { 1690, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x31c0110038ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1690 = MOV64ri32
19396 { 1708, 2, 1, 0, 6, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2c00020002ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1708 = MOV8ri
include/llvm/CodeGen/MachineInstr.h 750 return hasProperty(MCID::MoveImm, Type);
include/llvm/MC/MCInstrDesc.h 334 bool isMoveImmediate() const { return Flags & (1ULL << MCID::MoveImm); }