gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc

reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
namespace llvm {

namespace WebAssembly {
  enum {
    PHI	= 0,
    INLINEASM	= 1,
    INLINEASM_BR	= 2,
    CFI_INSTRUCTION	= 3,
    EH_LABEL	= 4,
    GC_LABEL	= 5,
    ANNOTATION_LABEL	= 6,
    KILL	= 7,
    EXTRACT_SUBREG	= 8,
    INSERT_SUBREG	= 9,
    IMPLICIT_DEF	= 10,
    SUBREG_TO_REG	= 11,
    COPY_TO_REGCLASS	= 12,
    DBG_VALUE	= 13,
    DBG_LABEL	= 14,
    REG_SEQUENCE	= 15,
    COPY	= 16,
    BUNDLE	= 17,
    LIFETIME_START	= 18,
    LIFETIME_END	= 19,
    STACKMAP	= 20,
    FENTRY_CALL	= 21,
    PATCHPOINT	= 22,
    LOAD_STACK_GUARD	= 23,
    STATEPOINT	= 24,
    LOCAL_ESCAPE	= 25,
    FAULTING_OP	= 26,
    PATCHABLE_OP	= 27,
    PATCHABLE_FUNCTION_ENTER	= 28,
    PATCHABLE_RET	= 29,
    PATCHABLE_FUNCTION_EXIT	= 30,
    PATCHABLE_TAIL_CALL	= 31,
    PATCHABLE_EVENT_CALL	= 32,
    PATCHABLE_TYPED_EVENT_CALL	= 33,
    ICALL_BRANCH_FUNNEL	= 34,
    G_ADD	= 35,
    G_SUB	= 36,
    G_MUL	= 37,
    G_SDIV	= 38,
    G_UDIV	= 39,
    G_SREM	= 40,
    G_UREM	= 41,
    G_AND	= 42,
    G_OR	= 43,
    G_XOR	= 44,
    G_IMPLICIT_DEF	= 45,
    G_PHI	= 46,
    G_FRAME_INDEX	= 47,
    G_GLOBAL_VALUE	= 48,
    G_EXTRACT	= 49,
    G_UNMERGE_VALUES	= 50,
    G_INSERT	= 51,
    G_MERGE_VALUES	= 52,
    G_BUILD_VECTOR	= 53,
    G_BUILD_VECTOR_TRUNC	= 54,
    G_CONCAT_VECTORS	= 55,
    G_PTRTOINT	= 56,
    G_INTTOPTR	= 57,
    G_BITCAST	= 58,
    G_INTRINSIC_TRUNC	= 59,
    G_INTRINSIC_ROUND	= 60,
    G_LOAD	= 61,
    G_SEXTLOAD	= 62,
    G_ZEXTLOAD	= 63,
    G_INDEXED_LOAD	= 64,
    G_INDEXED_SEXTLOAD	= 65,
    G_INDEXED_ZEXTLOAD	= 66,
    G_STORE	= 67,
    G_INDEXED_STORE	= 68,
    G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 69,
    G_ATOMIC_CMPXCHG	= 70,
    G_ATOMICRMW_XCHG	= 71,
    G_ATOMICRMW_ADD	= 72,
    G_ATOMICRMW_SUB	= 73,
    G_ATOMICRMW_AND	= 74,
    G_ATOMICRMW_NAND	= 75,
    G_ATOMICRMW_OR	= 76,
    G_ATOMICRMW_XOR	= 77,
    G_ATOMICRMW_MAX	= 78,
    G_ATOMICRMW_MIN	= 79,
    G_ATOMICRMW_UMAX	= 80,
    G_ATOMICRMW_UMIN	= 81,
    G_ATOMICRMW_FADD	= 82,
    G_ATOMICRMW_FSUB	= 83,
    G_FENCE	= 84,
    G_BRCOND	= 85,
    G_BRINDIRECT	= 86,
    G_INTRINSIC	= 87,
    G_INTRINSIC_W_SIDE_EFFECTS	= 88,
    G_ANYEXT	= 89,
    G_TRUNC	= 90,
    G_CONSTANT	= 91,
    G_FCONSTANT	= 92,
    G_VASTART	= 93,
    G_VAARG	= 94,
    G_SEXT	= 95,
    G_SEXT_INREG	= 96,
    G_ZEXT	= 97,
    G_SHL	= 98,
    G_LSHR	= 99,
    G_ASHR	= 100,
    G_ICMP	= 101,
    G_FCMP	= 102,
    G_SELECT	= 103,
    G_UADDO	= 104,
    G_UADDE	= 105,
    G_USUBO	= 106,
    G_USUBE	= 107,
    G_SADDO	= 108,
    G_SADDE	= 109,
    G_SSUBO	= 110,
    G_SSUBE	= 111,
    G_UMULO	= 112,
    G_SMULO	= 113,
    G_UMULH	= 114,
    G_SMULH	= 115,
    G_FADD	= 116,
    G_FSUB	= 117,
    G_FMUL	= 118,
    G_FMA	= 119,
    G_FMAD	= 120,
    G_FDIV	= 121,
    G_FREM	= 122,
    G_FPOW	= 123,
    G_FEXP	= 124,
    G_FEXP2	= 125,
    G_FLOG	= 126,
    G_FLOG2	= 127,
    G_FLOG10	= 128,
    G_FNEG	= 129,
    G_FPEXT	= 130,
    G_FPTRUNC	= 131,
    G_FPTOSI	= 132,
    G_FPTOUI	= 133,
    G_SITOFP	= 134,
    G_UITOFP	= 135,
    G_FABS	= 136,
    G_FCOPYSIGN	= 137,
    G_FCANONICALIZE	= 138,
    G_FMINNUM	= 139,
    G_FMAXNUM	= 140,
    G_FMINNUM_IEEE	= 141,
    G_FMAXNUM_IEEE	= 142,
    G_FMINIMUM	= 143,
    G_FMAXIMUM	= 144,
    G_GEP	= 145,
    G_PTR_MASK	= 146,
    G_SMIN	= 147,
    G_SMAX	= 148,
    G_UMIN	= 149,
    G_UMAX	= 150,
    G_BR	= 151,
    G_BRJT	= 152,
    G_INSERT_VECTOR_ELT	= 153,
    G_EXTRACT_VECTOR_ELT	= 154,
    G_SHUFFLE_VECTOR	= 155,
    G_CTTZ	= 156,
    G_CTTZ_ZERO_UNDEF	= 157,
    G_CTLZ	= 158,
    G_CTLZ_ZERO_UNDEF	= 159,
    G_CTPOP	= 160,
    G_BSWAP	= 161,
    G_BITREVERSE	= 162,
    G_FCEIL	= 163,
    G_FCOS	= 164,
    G_FSIN	= 165,
    G_FSQRT	= 166,
    G_FFLOOR	= 167,
    G_FRINT	= 168,
    G_FNEARBYINT	= 169,
    G_ADDRSPACE_CAST	= 170,
    G_BLOCK_ADDR	= 171,
    G_JUMP_TABLE	= 172,
    G_DYN_STACKALLOC	= 173,
    CATCHRET	= 174,
    CATCHRET_S	= 175,
    CLEANUPRET	= 176,
    CLEANUPRET_S	= 177,
    COMPILER_FENCE	= 178,
    COMPILER_FENCE_S	= 179,
    RETHROW_IN_CATCH	= 180,
    RETHROW_IN_CATCH_S	= 181,
    ABS_F32	= 182,
    ABS_F32_S	= 183,
    ABS_F64	= 184,
    ABS_F64_S	= 185,
    ABS_v2f64	= 186,
    ABS_v2f64_S	= 187,
    ABS_v4f32	= 188,
    ABS_v4f32_S	= 189,
    ADD_F32	= 190,
    ADD_F32_S	= 191,
    ADD_F64	= 192,
    ADD_F64_S	= 193,
    ADD_I32	= 194,
    ADD_I32_S	= 195,
    ADD_I64	= 196,
    ADD_I64_S	= 197,
    ADD_SAT_S_v16i8	= 198,
    ADD_SAT_S_v16i8_S	= 199,
    ADD_SAT_S_v8i16	= 200,
    ADD_SAT_S_v8i16_S	= 201,
    ADD_SAT_U_v16i8	= 202,
    ADD_SAT_U_v16i8_S	= 203,
    ADD_SAT_U_v8i16	= 204,
    ADD_SAT_U_v8i16_S	= 205,
    ADD_v16i8	= 206,
    ADD_v16i8_S	= 207,
    ADD_v2f64	= 208,
    ADD_v2f64_S	= 209,
    ADD_v2i64	= 210,
    ADD_v2i64_S	= 211,
    ADD_v4f32	= 212,
    ADD_v4f32_S	= 213,
    ADD_v4i32	= 214,
    ADD_v4i32_S	= 215,
    ADD_v8i16	= 216,
    ADD_v8i16_S	= 217,
    ADJCALLSTACKDOWN	= 218,
    ADJCALLSTACKDOWN_S	= 219,
    ADJCALLSTACKUP	= 220,
    ADJCALLSTACKUP_S	= 221,
    ALLTRUE_v16i8	= 222,
    ALLTRUE_v16i8_S	= 223,
    ALLTRUE_v2i64	= 224,
    ALLTRUE_v2i64_S	= 225,
    ALLTRUE_v4i32	= 226,
    ALLTRUE_v4i32_S	= 227,
    ALLTRUE_v8i16	= 228,
    ALLTRUE_v8i16_S	= 229,
    ANDNOT_v16i8	= 230,
    ANDNOT_v16i8_S	= 231,
    ANDNOT_v2i64	= 232,
    ANDNOT_v2i64_S	= 233,
    ANDNOT_v4i32	= 234,
    ANDNOT_v4i32_S	= 235,
    ANDNOT_v8i16	= 236,
    ANDNOT_v8i16_S	= 237,
    AND_I32	= 238,
    AND_I32_S	= 239,
    AND_I64	= 240,
    AND_I64_S	= 241,
    AND_v16i8	= 242,
    AND_v16i8_S	= 243,
    AND_v2i64	= 244,
    AND_v2i64_S	= 245,
    AND_v4i32	= 246,
    AND_v4i32_S	= 247,
    AND_v8i16	= 248,
    AND_v8i16_S	= 249,
    ANYTRUE_v16i8	= 250,
    ANYTRUE_v16i8_S	= 251,
    ANYTRUE_v2i64	= 252,
    ANYTRUE_v2i64_S	= 253,
    ANYTRUE_v4i32	= 254,
    ANYTRUE_v4i32_S	= 255,
    ANYTRUE_v8i16	= 256,
    ANYTRUE_v8i16_S	= 257,
    ARGUMENT_exnref	= 258,
    ARGUMENT_exnref_S	= 259,
    ARGUMENT_f32	= 260,
    ARGUMENT_f32_S	= 261,
    ARGUMENT_f64	= 262,
    ARGUMENT_f64_S	= 263,
    ARGUMENT_i32	= 264,
    ARGUMENT_i32_S	= 265,
    ARGUMENT_i64	= 266,
    ARGUMENT_i64_S	= 267,
    ARGUMENT_v16i8	= 268,
    ARGUMENT_v16i8_S	= 269,
    ARGUMENT_v2f64	= 270,
    ARGUMENT_v2f64_S	= 271,
    ARGUMENT_v2i64	= 272,
    ARGUMENT_v2i64_S	= 273,
    ARGUMENT_v4f32	= 274,
    ARGUMENT_v4f32_S	= 275,
    ARGUMENT_v4i32	= 276,
    ARGUMENT_v4i32_S	= 277,
    ARGUMENT_v8i16	= 278,
    ARGUMENT_v8i16_S	= 279,
    ATOMIC_FENCE	= 280,
    ATOMIC_FENCE_S	= 281,
    ATOMIC_LOAD16_U_I32	= 282,
    ATOMIC_LOAD16_U_I32_S	= 283,
    ATOMIC_LOAD16_U_I64	= 284,
    ATOMIC_LOAD16_U_I64_S	= 285,
    ATOMIC_LOAD32_U_I64	= 286,
    ATOMIC_LOAD32_U_I64_S	= 287,
    ATOMIC_LOAD8_U_I32	= 288,
    ATOMIC_LOAD8_U_I32_S	= 289,
    ATOMIC_LOAD8_U_I64	= 290,
    ATOMIC_LOAD8_U_I64_S	= 291,
    ATOMIC_LOAD_I32	= 292,
    ATOMIC_LOAD_I32_S	= 293,
    ATOMIC_LOAD_I64	= 294,
    ATOMIC_LOAD_I64_S	= 295,
    ATOMIC_NOTIFY	= 296,
    ATOMIC_NOTIFY_S	= 297,
    ATOMIC_RMW16_U_ADD_I32	= 298,
    ATOMIC_RMW16_U_ADD_I32_S	= 299,
    ATOMIC_RMW16_U_ADD_I64	= 300,
    ATOMIC_RMW16_U_ADD_I64_S	= 301,
    ATOMIC_RMW16_U_AND_I32	= 302,
    ATOMIC_RMW16_U_AND_I32_S	= 303,
    ATOMIC_RMW16_U_AND_I64	= 304,
    ATOMIC_RMW16_U_AND_I64_S	= 305,
    ATOMIC_RMW16_U_CMPXCHG_I32	= 306,
    ATOMIC_RMW16_U_CMPXCHG_I32_S	= 307,
    ATOMIC_RMW16_U_CMPXCHG_I64	= 308,
    ATOMIC_RMW16_U_CMPXCHG_I64_S	= 309,
    ATOMIC_RMW16_U_OR_I32	= 310,
    ATOMIC_RMW16_U_OR_I32_S	= 311,
    ATOMIC_RMW16_U_OR_I64	= 312,
    ATOMIC_RMW16_U_OR_I64_S	= 313,
    ATOMIC_RMW16_U_SUB_I32	= 314,
    ATOMIC_RMW16_U_SUB_I32_S	= 315,
    ATOMIC_RMW16_U_SUB_I64	= 316,
    ATOMIC_RMW16_U_SUB_I64_S	= 317,
    ATOMIC_RMW16_U_XCHG_I32	= 318,
    ATOMIC_RMW16_U_XCHG_I32_S	= 319,
    ATOMIC_RMW16_U_XCHG_I64	= 320,
    ATOMIC_RMW16_U_XCHG_I64_S	= 321,
    ATOMIC_RMW16_U_XOR_I32	= 322,
    ATOMIC_RMW16_U_XOR_I32_S	= 323,
    ATOMIC_RMW16_U_XOR_I64	= 324,
    ATOMIC_RMW16_U_XOR_I64_S	= 325,
    ATOMIC_RMW32_U_ADD_I64	= 326,
    ATOMIC_RMW32_U_ADD_I64_S	= 327,
    ATOMIC_RMW32_U_AND_I64	= 328,
    ATOMIC_RMW32_U_AND_I64_S	= 329,
    ATOMIC_RMW32_U_CMPXCHG_I64	= 330,
    ATOMIC_RMW32_U_CMPXCHG_I64_S	= 331,
    ATOMIC_RMW32_U_OR_I64	= 332,
    ATOMIC_RMW32_U_OR_I64_S	= 333,
    ATOMIC_RMW32_U_SUB_I64	= 334,
    ATOMIC_RMW32_U_SUB_I64_S	= 335,
    ATOMIC_RMW32_U_XCHG_I64	= 336,
    ATOMIC_RMW32_U_XCHG_I64_S	= 337,
    ATOMIC_RMW32_U_XOR_I64	= 338,
    ATOMIC_RMW32_U_XOR_I64_S	= 339,
    ATOMIC_RMW8_U_ADD_I32	= 340,
    ATOMIC_RMW8_U_ADD_I32_S	= 341,
    ATOMIC_RMW8_U_ADD_I64	= 342,
    ATOMIC_RMW8_U_ADD_I64_S	= 343,
    ATOMIC_RMW8_U_AND_I32	= 344,
    ATOMIC_RMW8_U_AND_I32_S	= 345,
    ATOMIC_RMW8_U_AND_I64	= 346,
    ATOMIC_RMW8_U_AND_I64_S	= 347,
    ATOMIC_RMW8_U_CMPXCHG_I32	= 348,
    ATOMIC_RMW8_U_CMPXCHG_I32_S	= 349,
    ATOMIC_RMW8_U_CMPXCHG_I64	= 350,
    ATOMIC_RMW8_U_CMPXCHG_I64_S	= 351,
    ATOMIC_RMW8_U_OR_I32	= 352,
    ATOMIC_RMW8_U_OR_I32_S	= 353,
    ATOMIC_RMW8_U_OR_I64	= 354,
    ATOMIC_RMW8_U_OR_I64_S	= 355,
    ATOMIC_RMW8_U_SUB_I32	= 356,
    ATOMIC_RMW8_U_SUB_I32_S	= 357,
    ATOMIC_RMW8_U_SUB_I64	= 358,
    ATOMIC_RMW8_U_SUB_I64_S	= 359,
    ATOMIC_RMW8_U_XCHG_I32	= 360,
    ATOMIC_RMW8_U_XCHG_I32_S	= 361,
    ATOMIC_RMW8_U_XCHG_I64	= 362,
    ATOMIC_RMW8_U_XCHG_I64_S	= 363,
    ATOMIC_RMW8_U_XOR_I32	= 364,
    ATOMIC_RMW8_U_XOR_I32_S	= 365,
    ATOMIC_RMW8_U_XOR_I64	= 366,
    ATOMIC_RMW8_U_XOR_I64_S	= 367,
    ATOMIC_RMW_ADD_I32	= 368,
    ATOMIC_RMW_ADD_I32_S	= 369,
    ATOMIC_RMW_ADD_I64	= 370,
    ATOMIC_RMW_ADD_I64_S	= 371,
    ATOMIC_RMW_AND_I32	= 372,
    ATOMIC_RMW_AND_I32_S	= 373,
    ATOMIC_RMW_AND_I64	= 374,
    ATOMIC_RMW_AND_I64_S	= 375,
    ATOMIC_RMW_CMPXCHG_I32	= 376,
    ATOMIC_RMW_CMPXCHG_I32_S	= 377,
    ATOMIC_RMW_CMPXCHG_I64	= 378,
    ATOMIC_RMW_CMPXCHG_I64_S	= 379,
    ATOMIC_RMW_OR_I32	= 380,
    ATOMIC_RMW_OR_I32_S	= 381,
    ATOMIC_RMW_OR_I64	= 382,
    ATOMIC_RMW_OR_I64_S	= 383,
    ATOMIC_RMW_SUB_I32	= 384,
    ATOMIC_RMW_SUB_I32_S	= 385,
    ATOMIC_RMW_SUB_I64	= 386,
    ATOMIC_RMW_SUB_I64_S	= 387,
    ATOMIC_RMW_XCHG_I32	= 388,
    ATOMIC_RMW_XCHG_I32_S	= 389,
    ATOMIC_RMW_XCHG_I64	= 390,
    ATOMIC_RMW_XCHG_I64_S	= 391,
    ATOMIC_RMW_XOR_I32	= 392,
    ATOMIC_RMW_XOR_I32_S	= 393,
    ATOMIC_RMW_XOR_I64	= 394,
    ATOMIC_RMW_XOR_I64_S	= 395,
    ATOMIC_STORE16_I32	= 396,
    ATOMIC_STORE16_I32_S	= 397,
    ATOMIC_STORE16_I64	= 398,
    ATOMIC_STORE16_I64_S	= 399,
    ATOMIC_STORE32_I64	= 400,
    ATOMIC_STORE32_I64_S	= 401,
    ATOMIC_STORE8_I32	= 402,
    ATOMIC_STORE8_I32_S	= 403,
    ATOMIC_STORE8_I64	= 404,
    ATOMIC_STORE8_I64_S	= 405,
    ATOMIC_STORE_I32	= 406,
    ATOMIC_STORE_I32_S	= 407,
    ATOMIC_STORE_I64	= 408,
    ATOMIC_STORE_I64_S	= 409,
    ATOMIC_WAIT_I32	= 410,
    ATOMIC_WAIT_I32_S	= 411,
    ATOMIC_WAIT_I64	= 412,
    ATOMIC_WAIT_I64_S	= 413,
    BITSELECT_v16i8	= 414,
    BITSELECT_v16i8_S	= 415,
    BITSELECT_v2f64	= 416,
    BITSELECT_v2f64_S	= 417,
    BITSELECT_v2i64	= 418,
    BITSELECT_v2i64_S	= 419,
    BITSELECT_v4f32	= 420,
    BITSELECT_v4f32_S	= 421,
    BITSELECT_v4i32	= 422,
    BITSELECT_v4i32_S	= 423,
    BITSELECT_v8i16	= 424,
    BITSELECT_v8i16_S	= 425,
    BLOCK	= 426,
    BLOCK_S	= 427,
    BR	= 428,
    BR_IF	= 429,
    BR_IF_S	= 430,
    BR_ON_EXN	= 431,
    BR_ON_EXN_S	= 432,
    BR_S	= 433,
    BR_TABLE_I32	= 434,
    BR_TABLE_I32_S	= 435,
    BR_TABLE_I64	= 436,
    BR_TABLE_I64_S	= 437,
    BR_UNLESS	= 438,
    BR_UNLESS_S	= 439,
    CALL_INDIRECT_VOID	= 440,
    CALL_INDIRECT_VOID_S	= 441,
    CALL_INDIRECT_exnref	= 442,
    CALL_INDIRECT_exnref_S	= 443,
    CALL_INDIRECT_f32	= 444,
    CALL_INDIRECT_f32_S	= 445,
    CALL_INDIRECT_f64	= 446,
    CALL_INDIRECT_f64_S	= 447,
    CALL_INDIRECT_i32	= 448,
    CALL_INDIRECT_i32_S	= 449,
    CALL_INDIRECT_i64	= 450,
    CALL_INDIRECT_i64_S	= 451,
    CALL_INDIRECT_v16i8	= 452,
    CALL_INDIRECT_v16i8_S	= 453,
    CALL_INDIRECT_v2f64	= 454,
    CALL_INDIRECT_v2f64_S	= 455,
    CALL_INDIRECT_v2i64	= 456,
    CALL_INDIRECT_v2i64_S	= 457,
    CALL_INDIRECT_v4f32	= 458,
    CALL_INDIRECT_v4f32_S	= 459,
    CALL_INDIRECT_v4i32	= 460,
    CALL_INDIRECT_v4i32_S	= 461,
    CALL_INDIRECT_v8i16	= 462,
    CALL_INDIRECT_v8i16_S	= 463,
    CALL_VOID	= 464,
    CALL_VOID_S	= 465,
    CALL_exnref	= 466,
    CALL_exnref_S	= 467,
    CALL_f32	= 468,
    CALL_f32_S	= 469,
    CALL_f64	= 470,
    CALL_f64_S	= 471,
    CALL_i32	= 472,
    CALL_i32_S	= 473,
    CALL_i64	= 474,
    CALL_i64_S	= 475,
    CALL_v16i8	= 476,
    CALL_v16i8_S	= 477,
    CALL_v2f64	= 478,
    CALL_v2f64_S	= 479,
    CALL_v2i64	= 480,
    CALL_v2i64_S	= 481,
    CALL_v4f32	= 482,
    CALL_v4f32_S	= 483,
    CALL_v4i32	= 484,
    CALL_v4i32_S	= 485,
    CALL_v8i16	= 486,
    CALL_v8i16_S	= 487,
    CATCH	= 488,
    CATCH_S	= 489,
    CEIL_F32	= 490,
    CEIL_F32_S	= 491,
    CEIL_F64	= 492,
    CEIL_F64_S	= 493,
    CLZ_I32	= 494,
    CLZ_I32_S	= 495,
    CLZ_I64	= 496,
    CLZ_I64_S	= 497,
    CONST_F32	= 498,
    CONST_F32_S	= 499,
    CONST_F64	= 500,
    CONST_F64_S	= 501,
    CONST_I32	= 502,
    CONST_I32_S	= 503,
    CONST_I64	= 504,
    CONST_I64_S	= 505,
    CONST_V128_v16i8	= 506,
    CONST_V128_v16i8_S	= 507,
    CONST_V128_v2f64	= 508,
    CONST_V128_v2f64_S	= 509,
    CONST_V128_v2i64	= 510,
    CONST_V128_v2i64_S	= 511,
    CONST_V128_v4f32	= 512,
    CONST_V128_v4f32_S	= 513,
    CONST_V128_v4i32	= 514,
    CONST_V128_v4i32_S	= 515,
    CONST_V128_v8i16	= 516,
    CONST_V128_v8i16_S	= 517,
    COPYSIGN_F32	= 518,
    COPYSIGN_F32_S	= 519,
    COPYSIGN_F64	= 520,
    COPYSIGN_F64_S	= 521,
    COPY_EXNREF	= 522,
    COPY_EXNREF_S	= 523,
    COPY_F32	= 524,
    COPY_F32_S	= 525,
    COPY_F64	= 526,
    COPY_F64_S	= 527,
    COPY_I32	= 528,
    COPY_I32_S	= 529,
    COPY_I64	= 530,
    COPY_I64_S	= 531,
    COPY_V128	= 532,
    COPY_V128_S	= 533,
    CTZ_I32	= 534,
    CTZ_I32_S	= 535,
    CTZ_I64	= 536,
    CTZ_I64_S	= 537,
    DATA_DROP	= 538,
    DATA_DROP_S	= 539,
    DIV_F32	= 540,
    DIV_F32_S	= 541,
    DIV_F64	= 542,
    DIV_F64_S	= 543,
    DIV_S_I32	= 544,
    DIV_S_I32_S	= 545,
    DIV_S_I64	= 546,
    DIV_S_I64_S	= 547,
    DIV_U_I32	= 548,
    DIV_U_I32_S	= 549,
    DIV_U_I64	= 550,
    DIV_U_I64_S	= 551,
    DIV_v2f64	= 552,
    DIV_v2f64_S	= 553,
    DIV_v4f32	= 554,
    DIV_v4f32_S	= 555,
    DROP_EXNREF	= 556,
    DROP_EXNREF_S	= 557,
    DROP_F32	= 558,
    DROP_F32_S	= 559,
    DROP_F64	= 560,
    DROP_F64_S	= 561,
    DROP_I32	= 562,
    DROP_I32_S	= 563,
    DROP_I64	= 564,
    DROP_I64_S	= 565,
    DROP_V128	= 566,
    DROP_V128_S	= 567,
    ELSE	= 568,
    ELSE_S	= 569,
    END	= 570,
    END_BLOCK	= 571,
    END_BLOCK_S	= 572,
    END_FUNCTION	= 573,
    END_FUNCTION_S	= 574,
    END_IF	= 575,
    END_IF_S	= 576,
    END_LOOP	= 577,
    END_LOOP_S	= 578,
    END_S	= 579,
    END_TRY	= 580,
    END_TRY_S	= 581,
    EQZ_I32	= 582,
    EQZ_I32_S	= 583,
    EQZ_I64	= 584,
    EQZ_I64_S	= 585,
    EQ_F32	= 586,
    EQ_F32_S	= 587,
    EQ_F64	= 588,
    EQ_F64_S	= 589,
    EQ_I32	= 590,
    EQ_I32_S	= 591,
    EQ_I64	= 592,
    EQ_I64_S	= 593,
    EQ_v16i8	= 594,
    EQ_v16i8_S	= 595,
    EQ_v2f64	= 596,
    EQ_v2f64_S	= 597,
    EQ_v4f32	= 598,
    EQ_v4f32_S	= 599,
    EQ_v4i32	= 600,
    EQ_v4i32_S	= 601,
    EQ_v8i16	= 602,
    EQ_v8i16_S	= 603,
    EXTRACT_EXCEPTION_I32	= 604,
    EXTRACT_EXCEPTION_I32_S	= 605,
    EXTRACT_LANE_v16i8_s	= 606,
    EXTRACT_LANE_v16i8_s_S	= 607,
    EXTRACT_LANE_v16i8_u	= 608,
    EXTRACT_LANE_v16i8_u_S	= 609,
    EXTRACT_LANE_v2f64	= 610,
    EXTRACT_LANE_v2f64_S	= 611,
    EXTRACT_LANE_v2i64	= 612,
    EXTRACT_LANE_v2i64_S	= 613,
    EXTRACT_LANE_v4f32	= 614,
    EXTRACT_LANE_v4f32_S	= 615,
    EXTRACT_LANE_v4i32	= 616,
    EXTRACT_LANE_v4i32_S	= 617,
    EXTRACT_LANE_v8i16_s	= 618,
    EXTRACT_LANE_v8i16_s_S	= 619,
    EXTRACT_LANE_v8i16_u	= 620,
    EXTRACT_LANE_v8i16_u_S	= 621,
    F32_CONVERT_S_I32	= 622,
    F32_CONVERT_S_I32_S	= 623,
    F32_CONVERT_S_I64	= 624,
    F32_CONVERT_S_I64_S	= 625,
    F32_CONVERT_U_I32	= 626,
    F32_CONVERT_U_I32_S	= 627,
    F32_CONVERT_U_I64	= 628,
    F32_CONVERT_U_I64_S	= 629,
    F32_DEMOTE_F64	= 630,
    F32_DEMOTE_F64_S	= 631,
    F32_REINTERPRET_I32	= 632,
    F32_REINTERPRET_I32_S	= 633,
    F64_CONVERT_S_I32	= 634,
    F64_CONVERT_S_I32_S	= 635,
    F64_CONVERT_S_I64	= 636,
    F64_CONVERT_S_I64_S	= 637,
    F64_CONVERT_U_I32	= 638,
    F64_CONVERT_U_I32_S	= 639,
    F64_CONVERT_U_I64	= 640,
    F64_CONVERT_U_I64_S	= 641,
    F64_PROMOTE_F32	= 642,
    F64_PROMOTE_F32_S	= 643,
    F64_REINTERPRET_I64	= 644,
    F64_REINTERPRET_I64_S	= 645,
    FALLTHROUGH_RETURN	= 646,
    FALLTHROUGH_RETURN_S	= 647,
    FLOOR_F32	= 648,
    FLOOR_F32_S	= 649,
    FLOOR_F64	= 650,
    FLOOR_F64_S	= 651,
    FP_TO_SINT_I32_F32	= 652,
    FP_TO_SINT_I32_F32_S	= 653,
    FP_TO_SINT_I32_F64	= 654,
    FP_TO_SINT_I32_F64_S	= 655,
    FP_TO_SINT_I64_F32	= 656,
    FP_TO_SINT_I64_F32_S	= 657,
    FP_TO_SINT_I64_F64	= 658,
    FP_TO_SINT_I64_F64_S	= 659,
    FP_TO_UINT_I32_F32	= 660,
    FP_TO_UINT_I32_F32_S	= 661,
    FP_TO_UINT_I32_F64	= 662,
    FP_TO_UINT_I32_F64_S	= 663,
    FP_TO_UINT_I64_F32	= 664,
    FP_TO_UINT_I64_F32_S	= 665,
    FP_TO_UINT_I64_F64	= 666,
    FP_TO_UINT_I64_F64_S	= 667,
    GE_F32	= 668,
    GE_F32_S	= 669,
    GE_F64	= 670,
    GE_F64_S	= 671,
    GE_S_I32	= 672,
    GE_S_I32_S	= 673,
    GE_S_I64	= 674,
    GE_S_I64_S	= 675,
    GE_S_v16i8	= 676,
    GE_S_v16i8_S	= 677,
    GE_S_v4i32	= 678,
    GE_S_v4i32_S	= 679,
    GE_S_v8i16	= 680,
    GE_S_v8i16_S	= 681,
    GE_U_I32	= 682,
    GE_U_I32_S	= 683,
    GE_U_I64	= 684,
    GE_U_I64_S	= 685,
    GE_U_v16i8	= 686,
    GE_U_v16i8_S	= 687,
    GE_U_v4i32	= 688,
    GE_U_v4i32_S	= 689,
    GE_U_v8i16	= 690,
    GE_U_v8i16_S	= 691,
    GE_v2f64	= 692,
    GE_v2f64_S	= 693,
    GE_v4f32	= 694,
    GE_v4f32_S	= 695,
    GLOBAL_GET_EXNREF	= 696,
    GLOBAL_GET_EXNREF_S	= 697,
    GLOBAL_GET_F32	= 698,
    GLOBAL_GET_F32_S	= 699,
    GLOBAL_GET_F64	= 700,
    GLOBAL_GET_F64_S	= 701,
    GLOBAL_GET_I32	= 702,
    GLOBAL_GET_I32_S	= 703,
    GLOBAL_GET_I64	= 704,
    GLOBAL_GET_I64_S	= 705,
    GLOBAL_GET_V128	= 706,
    GLOBAL_GET_V128_S	= 707,
    GLOBAL_SET_EXNREF	= 708,
    GLOBAL_SET_EXNREF_S	= 709,
    GLOBAL_SET_F32	= 710,
    GLOBAL_SET_F32_S	= 711,
    GLOBAL_SET_F64	= 712,
    GLOBAL_SET_F64_S	= 713,
    GLOBAL_SET_I32	= 714,
    GLOBAL_SET_I32_S	= 715,
    GLOBAL_SET_I64	= 716,
    GLOBAL_SET_I64_S	= 717,
    GLOBAL_SET_V128	= 718,
    GLOBAL_SET_V128_S	= 719,
    GT_F32	= 720,
    GT_F32_S	= 721,
    GT_F64	= 722,
    GT_F64_S	= 723,
    GT_S_I32	= 724,
    GT_S_I32_S	= 725,
    GT_S_I64	= 726,
    GT_S_I64_S	= 727,
    GT_S_v16i8	= 728,
    GT_S_v16i8_S	= 729,
    GT_S_v4i32	= 730,
    GT_S_v4i32_S	= 731,
    GT_S_v8i16	= 732,
    GT_S_v8i16_S	= 733,
    GT_U_I32	= 734,
    GT_U_I32_S	= 735,
    GT_U_I64	= 736,
    GT_U_I64_S	= 737,
    GT_U_v16i8	= 738,
    GT_U_v16i8_S	= 739,
    GT_U_v4i32	= 740,
    GT_U_v4i32_S	= 741,
    GT_U_v8i16	= 742,
    GT_U_v8i16_S	= 743,
    GT_v2f64	= 744,
    GT_v2f64_S	= 745,
    GT_v4f32	= 746,
    GT_v4f32_S	= 747,
    I32_EXTEND16_S_I32	= 748,
    I32_EXTEND16_S_I32_S	= 749,
    I32_EXTEND8_S_I32	= 750,
    I32_EXTEND8_S_I32_S	= 751,
    I32_REINTERPRET_F32	= 752,
    I32_REINTERPRET_F32_S	= 753,
    I32_TRUNC_S_F32	= 754,
    I32_TRUNC_S_F32_S	= 755,
    I32_TRUNC_S_F64	= 756,
    I32_TRUNC_S_F64_S	= 757,
    I32_TRUNC_S_SAT_F32	= 758,
    I32_TRUNC_S_SAT_F32_S	= 759,
    I32_TRUNC_S_SAT_F64	= 760,
    I32_TRUNC_S_SAT_F64_S	= 761,
    I32_TRUNC_U_F32	= 762,
    I32_TRUNC_U_F32_S	= 763,
    I32_TRUNC_U_F64	= 764,
    I32_TRUNC_U_F64_S	= 765,
    I32_TRUNC_U_SAT_F32	= 766,
    I32_TRUNC_U_SAT_F32_S	= 767,
    I32_TRUNC_U_SAT_F64	= 768,
    I32_TRUNC_U_SAT_F64_S	= 769,
    I32_WRAP_I64	= 770,
    I32_WRAP_I64_S	= 771,
    I64_EXTEND16_S_I64	= 772,
    I64_EXTEND16_S_I64_S	= 773,
    I64_EXTEND32_S_I64	= 774,
    I64_EXTEND32_S_I64_S	= 775,
    I64_EXTEND8_S_I64	= 776,
    I64_EXTEND8_S_I64_S	= 777,
    I64_EXTEND_S_I32	= 778,
    I64_EXTEND_S_I32_S	= 779,
    I64_EXTEND_U_I32	= 780,
    I64_EXTEND_U_I32_S	= 781,
    I64_REINTERPRET_F64	= 782,
    I64_REINTERPRET_F64_S	= 783,
    I64_TRUNC_S_F32	= 784,
    I64_TRUNC_S_F32_S	= 785,
    I64_TRUNC_S_F64	= 786,
    I64_TRUNC_S_F64_S	= 787,
    I64_TRUNC_S_SAT_F32	= 788,
    I64_TRUNC_S_SAT_F32_S	= 789,
    I64_TRUNC_S_SAT_F64	= 790,
    I64_TRUNC_S_SAT_F64_S	= 791,
    I64_TRUNC_U_F32	= 792,
    I64_TRUNC_U_F32_S	= 793,
    I64_TRUNC_U_F64	= 794,
    I64_TRUNC_U_F64_S	= 795,
    I64_TRUNC_U_SAT_F32	= 796,
    I64_TRUNC_U_SAT_F32_S	= 797,
    I64_TRUNC_U_SAT_F64	= 798,
    I64_TRUNC_U_SAT_F64_S	= 799,
    IF	= 800,
    IF_S	= 801,
    LE_F32	= 802,
    LE_F32_S	= 803,
    LE_F64	= 804,
    LE_F64_S	= 805,
    LE_S_I32	= 806,
    LE_S_I32_S	= 807,
    LE_S_I64	= 808,
    LE_S_I64_S	= 809,
    LE_S_v16i8	= 810,
    LE_S_v16i8_S	= 811,
    LE_S_v4i32	= 812,
    LE_S_v4i32_S	= 813,
    LE_S_v8i16	= 814,
    LE_S_v8i16_S	= 815,
    LE_U_I32	= 816,
    LE_U_I32_S	= 817,
    LE_U_I64	= 818,
    LE_U_I64_S	= 819,
    LE_U_v16i8	= 820,
    LE_U_v16i8_S	= 821,
    LE_U_v4i32	= 822,
    LE_U_v4i32_S	= 823,
    LE_U_v8i16	= 824,
    LE_U_v8i16_S	= 825,
    LE_v2f64	= 826,
    LE_v2f64_S	= 827,
    LE_v4f32	= 828,
    LE_v4f32_S	= 829,
    LOAD16_S_I32	= 830,
    LOAD16_S_I32_S	= 831,
    LOAD16_S_I64	= 832,
    LOAD16_S_I64_S	= 833,
    LOAD16_U_I32	= 834,
    LOAD16_U_I32_S	= 835,
    LOAD16_U_I64	= 836,
    LOAD16_U_I64_S	= 837,
    LOAD32_S_I64	= 838,
    LOAD32_S_I64_S	= 839,
    LOAD32_U_I64	= 840,
    LOAD32_U_I64_S	= 841,
    LOAD8_S_I32	= 842,
    LOAD8_S_I32_S	= 843,
    LOAD8_S_I64	= 844,
    LOAD8_S_I64_S	= 845,
    LOAD8_U_I32	= 846,
    LOAD8_U_I32_S	= 847,
    LOAD8_U_I64	= 848,
    LOAD8_U_I64_S	= 849,
    LOAD_EXTEND_S_v2i64	= 850,
    LOAD_EXTEND_S_v2i64_S	= 851,
    LOAD_EXTEND_S_v4i32	= 852,
    LOAD_EXTEND_S_v4i32_S	= 853,
    LOAD_EXTEND_S_v8i16	= 854,
    LOAD_EXTEND_S_v8i16_S	= 855,
    LOAD_EXTEND_U_v2i64	= 856,
    LOAD_EXTEND_U_v2i64_S	= 857,
    LOAD_EXTEND_U_v4i32	= 858,
    LOAD_EXTEND_U_v4i32_S	= 859,
    LOAD_EXTEND_U_v8i16	= 860,
    LOAD_EXTEND_U_v8i16_S	= 861,
    LOAD_F32	= 862,
    LOAD_F32_S	= 863,
    LOAD_F64	= 864,
    LOAD_F64_S	= 865,
    LOAD_I32	= 866,
    LOAD_I32_S	= 867,
    LOAD_I64	= 868,
    LOAD_I64_S	= 869,
    LOAD_SPLAT_v16x8	= 870,
    LOAD_SPLAT_v16x8_S	= 871,
    LOAD_SPLAT_v32x4	= 872,
    LOAD_SPLAT_v32x4_S	= 873,
    LOAD_SPLAT_v64x2	= 874,
    LOAD_SPLAT_v64x2_S	= 875,
    LOAD_SPLAT_v8x16	= 876,
    LOAD_SPLAT_v8x16_S	= 877,
    LOAD_V128	= 878,
    LOAD_V128_S	= 879,
    LOCAL_GET_EXNREF	= 880,
    LOCAL_GET_EXNREF_S	= 881,
    LOCAL_GET_F32	= 882,
    LOCAL_GET_F32_S	= 883,
    LOCAL_GET_F64	= 884,
    LOCAL_GET_F64_S	= 885,
    LOCAL_GET_I32	= 886,
    LOCAL_GET_I32_S	= 887,
    LOCAL_GET_I64	= 888,
    LOCAL_GET_I64_S	= 889,
    LOCAL_GET_V128	= 890,
    LOCAL_GET_V128_S	= 891,
    LOCAL_SET_EXNREF	= 892,
    LOCAL_SET_EXNREF_S	= 893,
    LOCAL_SET_F32	= 894,
    LOCAL_SET_F32_S	= 895,
    LOCAL_SET_F64	= 896,
    LOCAL_SET_F64_S	= 897,
    LOCAL_SET_I32	= 898,
    LOCAL_SET_I32_S	= 899,
    LOCAL_SET_I64	= 900,
    LOCAL_SET_I64_S	= 901,
    LOCAL_SET_V128	= 902,
    LOCAL_SET_V128_S	= 903,
    LOCAL_TEE_EXNREF	= 904,
    LOCAL_TEE_EXNREF_S	= 905,
    LOCAL_TEE_F32	= 906,
    LOCAL_TEE_F32_S	= 907,
    LOCAL_TEE_F64	= 908,
    LOCAL_TEE_F64_S	= 909,
    LOCAL_TEE_I32	= 910,
    LOCAL_TEE_I32_S	= 911,
    LOCAL_TEE_I64	= 912,
    LOCAL_TEE_I64_S	= 913,
    LOCAL_TEE_V128	= 914,
    LOCAL_TEE_V128_S	= 915,
    LOOP	= 916,
    LOOP_S	= 917,
    LT_F32	= 918,
    LT_F32_S	= 919,
    LT_F64	= 920,
    LT_F64_S	= 921,
    LT_S_I32	= 922,
    LT_S_I32_S	= 923,
    LT_S_I64	= 924,
    LT_S_I64_S	= 925,
    LT_S_v16i8	= 926,
    LT_S_v16i8_S	= 927,
    LT_S_v4i32	= 928,
    LT_S_v4i32_S	= 929,
    LT_S_v8i16	= 930,
    LT_S_v8i16_S	= 931,
    LT_U_I32	= 932,
    LT_U_I32_S	= 933,
    LT_U_I64	= 934,
    LT_U_I64_S	= 935,
    LT_U_v16i8	= 936,
    LT_U_v16i8_S	= 937,
    LT_U_v4i32	= 938,
    LT_U_v4i32_S	= 939,
    LT_U_v8i16	= 940,
    LT_U_v8i16_S	= 941,
    LT_v2f64	= 942,
    LT_v2f64_S	= 943,
    LT_v4f32	= 944,
    LT_v4f32_S	= 945,
    MAX_F32	= 946,
    MAX_F32_S	= 947,
    MAX_F64	= 948,
    MAX_F64_S	= 949,
    MAX_v2f64	= 950,
    MAX_v2f64_S	= 951,
    MAX_v4f32	= 952,
    MAX_v4f32_S	= 953,
    MEMORY_COPY	= 954,
    MEMORY_COPY_S	= 955,
    MEMORY_FILL	= 956,
    MEMORY_FILL_S	= 957,
    MEMORY_GROW_I32	= 958,
    MEMORY_GROW_I32_S	= 959,
    MEMORY_INIT	= 960,
    MEMORY_INIT_S	= 961,
    MEMORY_SIZE_I32	= 962,
    MEMORY_SIZE_I32_S	= 963,
    MIN_F32	= 964,
    MIN_F32_S	= 965,
    MIN_F64	= 966,
    MIN_F64_S	= 967,
    MIN_v2f64	= 968,
    MIN_v2f64_S	= 969,
    MIN_v4f32	= 970,
    MIN_v4f32_S	= 971,
    MUL_F32	= 972,
    MUL_F32_S	= 973,
    MUL_F64	= 974,
    MUL_F64_S	= 975,
    MUL_I32	= 976,
    MUL_I32_S	= 977,
    MUL_I64	= 978,
    MUL_I64_S	= 979,
    MUL_v16i8	= 980,
    MUL_v16i8_S	= 981,
    MUL_v2f64	= 982,
    MUL_v2f64_S	= 983,
    MUL_v4f32	= 984,
    MUL_v4f32_S	= 985,
    MUL_v4i32	= 986,
    MUL_v4i32_S	= 987,
    MUL_v8i16	= 988,
    MUL_v8i16_S	= 989,
    NARROW_S_v16i8	= 990,
    NARROW_S_v16i8_S	= 991,
    NARROW_S_v8i16	= 992,
    NARROW_S_v8i16_S	= 993,
    NARROW_U_v16i8	= 994,
    NARROW_U_v16i8_S	= 995,
    NARROW_U_v8i16	= 996,
    NARROW_U_v8i16_S	= 997,
    NEAREST_F32	= 998,
    NEAREST_F32_S	= 999,
    NEAREST_F64	= 1000,
    NEAREST_F64_S	= 1001,
    NEG_F32	= 1002,
    NEG_F32_S	= 1003,
    NEG_F64	= 1004,
    NEG_F64_S	= 1005,
    NEG_v16i8	= 1006,
    NEG_v16i8_S	= 1007,
    NEG_v2f64	= 1008,
    NEG_v2f64_S	= 1009,
    NEG_v2i64	= 1010,
    NEG_v2i64_S	= 1011,
    NEG_v4f32	= 1012,
    NEG_v4f32_S	= 1013,
    NEG_v4i32	= 1014,
    NEG_v4i32_S	= 1015,
    NEG_v8i16	= 1016,
    NEG_v8i16_S	= 1017,
    NE_F32	= 1018,
    NE_F32_S	= 1019,
    NE_F64	= 1020,
    NE_F64_S	= 1021,
    NE_I32	= 1022,
    NE_I32_S	= 1023,
    NE_I64	= 1024,
    NE_I64_S	= 1025,
    NE_v16i8	= 1026,
    NE_v16i8_S	= 1027,
    NE_v2f64	= 1028,
    NE_v2f64_S	= 1029,
    NE_v4f32	= 1030,
    NE_v4f32_S	= 1031,
    NE_v4i32	= 1032,
    NE_v4i32_S	= 1033,
    NE_v8i16	= 1034,
    NE_v8i16_S	= 1035,
    NOP	= 1036,
    NOP_S	= 1037,
    NOT_v16i8	= 1038,
    NOT_v16i8_S	= 1039,
    NOT_v2i64	= 1040,
    NOT_v2i64_S	= 1041,
    NOT_v4i32	= 1042,
    NOT_v4i32_S	= 1043,
    NOT_v8i16	= 1044,
    NOT_v8i16_S	= 1045,
    OR_I32	= 1046,
    OR_I32_S	= 1047,
    OR_I64	= 1048,
    OR_I64_S	= 1049,
    OR_v16i8	= 1050,
    OR_v16i8_S	= 1051,
    OR_v2i64	= 1052,
    OR_v2i64_S	= 1053,
    OR_v4i32	= 1054,
    OR_v4i32_S	= 1055,
    OR_v8i16	= 1056,
    OR_v8i16_S	= 1057,
    PCALL_INDIRECT_VOID	= 1058,
    PCALL_INDIRECT_VOID_S	= 1059,
    PCALL_INDIRECT_exnref	= 1060,
    PCALL_INDIRECT_exnref_S	= 1061,
    PCALL_INDIRECT_f32	= 1062,
    PCALL_INDIRECT_f32_S	= 1063,
    PCALL_INDIRECT_f64	= 1064,
    PCALL_INDIRECT_f64_S	= 1065,
    PCALL_INDIRECT_i32	= 1066,
    PCALL_INDIRECT_i32_S	= 1067,
    PCALL_INDIRECT_i64	= 1068,
    PCALL_INDIRECT_i64_S	= 1069,
    PCALL_INDIRECT_v16i8	= 1070,
    PCALL_INDIRECT_v16i8_S	= 1071,
    PCALL_INDIRECT_v2f64	= 1072,
    PCALL_INDIRECT_v2f64_S	= 1073,
    PCALL_INDIRECT_v2i64	= 1074,
    PCALL_INDIRECT_v2i64_S	= 1075,
    PCALL_INDIRECT_v4f32	= 1076,
    PCALL_INDIRECT_v4f32_S	= 1077,
    PCALL_INDIRECT_v4i32	= 1078,
    PCALL_INDIRECT_v4i32_S	= 1079,
    PCALL_INDIRECT_v8i16	= 1080,
    PCALL_INDIRECT_v8i16_S	= 1081,
    POPCNT_I32	= 1082,
    POPCNT_I32_S	= 1083,
    POPCNT_I64	= 1084,
    POPCNT_I64_S	= 1085,
    PRET_CALL_INDIRECT	= 1086,
    PRET_CALL_INDIRECT_S	= 1087,
    QFMA_v2f64	= 1088,
    QFMA_v2f64_S	= 1089,
    QFMA_v4f32	= 1090,
    QFMA_v4f32_S	= 1091,
    QFMS_v2f64	= 1092,
    QFMS_v2f64_S	= 1093,
    QFMS_v4f32	= 1094,
    QFMS_v4f32_S	= 1095,
    REM_S_I32	= 1096,
    REM_S_I32_S	= 1097,
    REM_S_I64	= 1098,
    REM_S_I64_S	= 1099,
    REM_U_I32	= 1100,
    REM_U_I32_S	= 1101,
    REM_U_I64	= 1102,
    REM_U_I64_S	= 1103,
    REPLACE_LANE_v16i8	= 1104,
    REPLACE_LANE_v16i8_S	= 1105,
    REPLACE_LANE_v2f64	= 1106,
    REPLACE_LANE_v2f64_S	= 1107,
    REPLACE_LANE_v2i64	= 1108,
    REPLACE_LANE_v2i64_S	= 1109,
    REPLACE_LANE_v4f32	= 1110,
    REPLACE_LANE_v4f32_S	= 1111,
    REPLACE_LANE_v4i32	= 1112,
    REPLACE_LANE_v4i32_S	= 1113,
    REPLACE_LANE_v8i16	= 1114,
    REPLACE_LANE_v8i16_S	= 1115,
    RETHROW	= 1116,
    RETHROW_S	= 1117,
    RETURN	= 1118,
    RETURN_S	= 1119,
    RET_CALL	= 1120,
    RET_CALL_INDIRECT	= 1121,
    RET_CALL_INDIRECT_S	= 1122,
    RET_CALL_S	= 1123,
    ROTL_I32	= 1124,
    ROTL_I32_S	= 1125,
    ROTL_I64	= 1126,
    ROTL_I64_S	= 1127,
    ROTR_I32	= 1128,
    ROTR_I32_S	= 1129,
    ROTR_I64	= 1130,
    ROTR_I64_S	= 1131,
    SELECT_EXNREF	= 1132,
    SELECT_EXNREF_S	= 1133,
    SELECT_F32	= 1134,
    SELECT_F32_S	= 1135,
    SELECT_F64	= 1136,
    SELECT_F64_S	= 1137,
    SELECT_I32	= 1138,
    SELECT_I32_S	= 1139,
    SELECT_I64	= 1140,
    SELECT_I64_S	= 1141,
    SHL_I32	= 1142,
    SHL_I32_S	= 1143,
    SHL_I64	= 1144,
    SHL_I64_S	= 1145,
    SHL_v16i8	= 1146,
    SHL_v16i8_S	= 1147,
    SHL_v2i64	= 1148,
    SHL_v2i64_S	= 1149,
    SHL_v4i32	= 1150,
    SHL_v4i32_S	= 1151,
    SHL_v8i16	= 1152,
    SHL_v8i16_S	= 1153,
    SHR_S_I32	= 1154,
    SHR_S_I32_S	= 1155,
    SHR_S_I64	= 1156,
    SHR_S_I64_S	= 1157,
    SHR_S_v16i8	= 1158,
    SHR_S_v16i8_S	= 1159,
    SHR_S_v2i64	= 1160,
    SHR_S_v2i64_S	= 1161,
    SHR_S_v4i32	= 1162,
    SHR_S_v4i32_S	= 1163,
    SHR_S_v8i16	= 1164,
    SHR_S_v8i16_S	= 1165,
    SHR_U_I32	= 1166,
    SHR_U_I32_S	= 1167,
    SHR_U_I64	= 1168,
    SHR_U_I64_S	= 1169,
    SHR_U_v16i8	= 1170,
    SHR_U_v16i8_S	= 1171,
    SHR_U_v2i64	= 1172,
    SHR_U_v2i64_S	= 1173,
    SHR_U_v4i32	= 1174,
    SHR_U_v4i32_S	= 1175,
    SHR_U_v8i16	= 1176,
    SHR_U_v8i16_S	= 1177,
    SHUFFLE	= 1178,
    SHUFFLE_S	= 1179,
    SPLAT_v16i8	= 1180,
    SPLAT_v16i8_S	= 1181,
    SPLAT_v2f64	= 1182,
    SPLAT_v2f64_S	= 1183,
    SPLAT_v2i64	= 1184,
    SPLAT_v2i64_S	= 1185,
    SPLAT_v4f32	= 1186,
    SPLAT_v4f32_S	= 1187,
    SPLAT_v4i32	= 1188,
    SPLAT_v4i32_S	= 1189,
    SPLAT_v8i16	= 1190,
    SPLAT_v8i16_S	= 1191,
    SQRT_F32	= 1192,
    SQRT_F32_S	= 1193,
    SQRT_F64	= 1194,
    SQRT_F64_S	= 1195,
    SQRT_v2f64	= 1196,
    SQRT_v2f64_S	= 1197,
    SQRT_v4f32	= 1198,
    SQRT_v4f32_S	= 1199,
    STORE16_I32	= 1200,
    STORE16_I32_S	= 1201,
    STORE16_I64	= 1202,
    STORE16_I64_S	= 1203,
    STORE32_I64	= 1204,
    STORE32_I64_S	= 1205,
    STORE8_I32	= 1206,
    STORE8_I32_S	= 1207,
    STORE8_I64	= 1208,
    STORE8_I64_S	= 1209,
    STORE_F32	= 1210,
    STORE_F32_S	= 1211,
    STORE_F64	= 1212,
    STORE_F64_S	= 1213,
    STORE_I32	= 1214,
    STORE_I32_S	= 1215,
    STORE_I64	= 1216,
    STORE_I64_S	= 1217,
    STORE_V128	= 1218,
    STORE_V128_S	= 1219,
    SUB_F32	= 1220,
    SUB_F32_S	= 1221,
    SUB_F64	= 1222,
    SUB_F64_S	= 1223,
    SUB_I32	= 1224,
    SUB_I32_S	= 1225,
    SUB_I64	= 1226,
    SUB_I64_S	= 1227,
    SUB_SAT_S_v16i8	= 1228,
    SUB_SAT_S_v16i8_S	= 1229,
    SUB_SAT_S_v8i16	= 1230,
    SUB_SAT_S_v8i16_S	= 1231,
    SUB_SAT_U_v16i8	= 1232,
    SUB_SAT_U_v16i8_S	= 1233,
    SUB_SAT_U_v8i16	= 1234,
    SUB_SAT_U_v8i16_S	= 1235,
    SUB_v16i8	= 1236,
    SUB_v16i8_S	= 1237,
    SUB_v2f64	= 1238,
    SUB_v2f64_S	= 1239,
    SUB_v2i64	= 1240,
    SUB_v2i64_S	= 1241,
    SUB_v4f32	= 1242,
    SUB_v4f32_S	= 1243,
    SUB_v4i32	= 1244,
    SUB_v4i32_S	= 1245,
    SUB_v8i16	= 1246,
    SUB_v8i16_S	= 1247,
    SWIZZLE	= 1248,
    SWIZZLE_S	= 1249,
    TEE_EXNREF	= 1250,
    TEE_EXNREF_S	= 1251,
    TEE_F32	= 1252,
    TEE_F32_S	= 1253,
    TEE_F64	= 1254,
    TEE_F64_S	= 1255,
    TEE_I32	= 1256,
    TEE_I32_S	= 1257,
    TEE_I64	= 1258,
    TEE_I64_S	= 1259,
    TEE_V128	= 1260,
    TEE_V128_S	= 1261,
    THROW	= 1262,
    THROW_S	= 1263,
    TRUNC_F32	= 1264,
    TRUNC_F32_S	= 1265,
    TRUNC_F64	= 1266,
    TRUNC_F64_S	= 1267,
    TRY	= 1268,
    TRY_S	= 1269,
    UNREACHABLE	= 1270,
    UNREACHABLE_S	= 1271,
    XOR_I32	= 1272,
    XOR_I32_S	= 1273,
    XOR_I64	= 1274,
    XOR_I64_S	= 1275,
    XOR_v16i8	= 1276,
    XOR_v16i8_S	= 1277,
    XOR_v2i64	= 1278,
    XOR_v2i64_S	= 1279,
    XOR_v4i32	= 1280,
    XOR_v4i32_S	= 1281,
    XOR_v8i16	= 1282,
    XOR_v8i16_S	= 1283,
    fp_to_sint_v2i64_v2f64	= 1284,
    fp_to_sint_v2i64_v2f64_S	= 1285,
    fp_to_sint_v4i32_v4f32	= 1286,
    fp_to_sint_v4i32_v4f32_S	= 1287,
    fp_to_uint_v2i64_v2f64	= 1288,
    fp_to_uint_v2i64_v2f64_S	= 1289,
    fp_to_uint_v4i32_v4f32	= 1290,
    fp_to_uint_v4i32_v4f32_S	= 1291,
    int_wasm_widen_high_signed_v4i32_v8i16	= 1292,
    int_wasm_widen_high_signed_v4i32_v8i16_S	= 1293,
    int_wasm_widen_high_signed_v8i16_v16i8	= 1294,
    int_wasm_widen_high_signed_v8i16_v16i8_S	= 1295,
    int_wasm_widen_high_unsigned_v4i32_v8i16	= 1296,
    int_wasm_widen_high_unsigned_v4i32_v8i16_S	= 1297,
    int_wasm_widen_high_unsigned_v8i16_v16i8	= 1298,
    int_wasm_widen_high_unsigned_v8i16_v16i8_S	= 1299,
    int_wasm_widen_low_signed_v4i32_v8i16	= 1300,
    int_wasm_widen_low_signed_v4i32_v8i16_S	= 1301,
    int_wasm_widen_low_signed_v8i16_v16i8	= 1302,
    int_wasm_widen_low_signed_v8i16_v16i8_S	= 1303,
    int_wasm_widen_low_unsigned_v4i32_v8i16	= 1304,
    int_wasm_widen_low_unsigned_v4i32_v8i16_S	= 1305,
    int_wasm_widen_low_unsigned_v8i16_v16i8	= 1306,
    int_wasm_widen_low_unsigned_v8i16_v16i8_S	= 1307,
    sint_to_fp_v2f64_v2i64	= 1308,
    sint_to_fp_v2f64_v2i64_S	= 1309,
    sint_to_fp_v4f32_v4i32	= 1310,
    sint_to_fp_v4f32_v4i32_S	= 1311,
    uint_to_fp_v2f64_v2i64	= 1312,
    uint_to_fp_v2f64_v2i64_S	= 1313,
    uint_to_fp_v4f32_v4i32	= 1314,
    uint_to_fp_v4f32_v4i32_S	= 1315,
    INSTRUCTION_LIST_END = 1316
  };

} // end namespace WebAssembly
} // end namespace llvm
#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM
namespace llvm {

namespace WebAssembly {
namespace Sched {
  enum {
    NoInstrModel	= 0,
    SCHED_LIST_END = 1
  };
} // end namespace Sched
} // end namespace WebAssembly
} // end namespace llvm
#endif // GET_INSTRINFO_SCHED_ENUM

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC
namespace llvm {

static const MCPhysReg ImplicitList1[] = { WebAssembly::ARGUMENTS, 0 };
static const MCPhysReg ImplicitList2[] = { WebAssembly::SP32, WebAssembly::SP64, 0 };
static const MCPhysReg ImplicitList3[] = { WebAssembly::VALUE_STACK, 0 };

static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo36[] = { { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, };
static const MCOperandInfo OperandInfo37[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo38[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo39[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo40[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo41[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo42[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo43[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo44[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo45[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo46[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo47[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo48[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo49[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo50[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo51[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo52[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo53[] = { { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, };
static const MCOperandInfo OperandInfo54[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo55[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo56[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo57[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo58[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo59[] = { { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo60[] = { { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo61[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo62[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo63[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo64[] = { { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, };
static const MCOperandInfo OperandInfo65[] = { { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, };
static const MCOperandInfo OperandInfo66[] = { { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo67[] = { { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_EVENT, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo68[] = { { -1, 0, WebAssembly::OPERAND_BASIC_BLOCK, 0 }, { -1, 0, WebAssembly::OPERAND_EVENT, 0 }, };
static const MCOperandInfo OperandInfo69[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo70[] = { { -1, 0, WebAssembly::OPERAND_BRLIST, 0 }, };
static const MCOperandInfo OperandInfo71[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo72[] = { { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo73[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo74[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo75[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo76[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo77[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo78[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_TYPEINDEX, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
static const MCOperandInfo OperandInfo79[] = { { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo80[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo81[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo82[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo83[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo84[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo85[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_FUNCTION32, 0 }, };
static const MCOperandInfo OperandInfo86[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo87[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo88[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo89[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, };
static const MCOperandInfo OperandInfo90[] = { { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, };
static const MCOperandInfo OperandInfo91[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, };
static const MCOperandInfo OperandInfo92[] = { { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, };
static const MCOperandInfo OperandInfo93[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, };
static const MCOperandInfo OperandInfo94[] = { { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, };
static const MCOperandInfo OperandInfo95[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, };
static const MCOperandInfo OperandInfo96[] = { { -1, 0, WebAssembly::OPERAND_I64IMM, 0 }, };
static const MCOperandInfo OperandInfo97[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo98[] = { { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo99[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, };
static const MCOperandInfo OperandInfo100[] = { { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F64IMM, 0 }, };
static const MCOperandInfo OperandInfo101[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, };
static const MCOperandInfo OperandInfo102[] = { { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I64IMM, 0 }, };
static const MCOperandInfo OperandInfo103[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, };
static const MCOperandInfo OperandInfo104[] = { { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_F32IMM, 0 }, };
static const MCOperandInfo OperandInfo105[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, };
static const MCOperandInfo OperandInfo106[] = { { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I32IMM, 0 }, };
static const MCOperandInfo OperandInfo107[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, };
static const MCOperandInfo OperandInfo108[] = { { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I16IMM, 0 }, };
static const MCOperandInfo OperandInfo109[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo110[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo111[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo112[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo113[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo114[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo115[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo116[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo117[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo118[] = { { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo119[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo120[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo121[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo122[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo123[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo124[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo125[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo126[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo127[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo128[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo129[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo130[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo131[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo132[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo133[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo134[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo135[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo136[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo137[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo138[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, };
static const MCOperandInfo OperandInfo139[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo140[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo141[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo142[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo143[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo144[] = { { -1, 0, WebAssembly::OPERAND_GLOBAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo145[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo146[] = { { -1, 0, WebAssembly::OPERAND_SIGNATURE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo147[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo148[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo149[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo150[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo151[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo152[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo153[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo154[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo155[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo156[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, };
static const MCOperandInfo OperandInfo157[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo158[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo159[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo160[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo161[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo162[] = { { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo163[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo164[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo165[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo166[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo167[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo168[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_LOCAL, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo169[] = { { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo170[] = { { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, };
static const MCOperandInfo OperandInfo171[] = { { -1, 0, WebAssembly::OPERAND_I32IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo172[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo173[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo174[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo175[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo176[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo177[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo178[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo179[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo180[] = { { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo181[] = { { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo182[] = { { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo183[] = { { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo184[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo185[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, { -1, 0, WebAssembly::OPERAND_VEC_I8IMM, 0 }, };
static const MCOperandInfo OperandInfo186[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo187[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::I64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo188[] = { { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo189[] = { { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo190[] = { { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::F64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo191[] = { { -1, 0, WebAssembly::OPERAND_P2ALIGN, 0 }, { -1, 0, WebAssembly::OPERAND_OFFSET32, 0 }, { WebAssembly::I32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::V128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo192[] = { { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { WebAssembly::EXNREFRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
static const MCOperandInfo OperandInfo193[] = { { -1, 0, WebAssembly::OPERAND_EVENT, 0 }, };

extern const MCInstrDesc WebAssemblyInsts[] = {
  { 0,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #0 = PHI
  { 1,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
  { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  { 3,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #3 = CFI_INSTRUCTION
  { 4,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #4 = EH_LABEL
  { 5,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #5 = GC_LABEL
  { 6,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = ANNOTATION_LABEL
  { 7,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #7 = KILL
  { 8,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #8 = EXTRACT_SUBREG
  { 9,	4,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #9 = INSERT_SUBREG
  { 10,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #10 = IMPLICIT_DEF
  { 11,	4,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #11 = SUBREG_TO_REG
  { 12,	3,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #12 = COPY_TO_REGCLASS
  { 13,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #13 = DBG_VALUE
  { 14,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #14 = DBG_LABEL
  { 15,	2,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #15 = REG_SEQUENCE
  { 16,	2,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #16 = COPY
  { 17,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #17 = BUNDLE
  { 18,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #18 = LIFETIME_START
  { 19,	1,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #19 = LIFETIME_END
  { 20,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #20 = STACKMAP
  { 21,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #21 = FENTRY_CALL
  { 22,	6,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #22 = PATCHPOINT
  { 23,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #23 = LOAD_STACK_GUARD
  { 24,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #24 = STATEPOINT
  { 25,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #25 = LOCAL_ESCAPE
  { 26,	1,	1,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #26 = FAULTING_OP
  { 27,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #27 = PATCHABLE_OP
  { 28,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #28 = PATCHABLE_FUNCTION_ENTER
  { 29,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #29 = PATCHABLE_RET
  { 30,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #30 = PATCHABLE_FUNCTION_EXIT
  { 31,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #31 = PATCHABLE_TAIL_CALL
  { 32,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #32 = PATCHABLE_EVENT_CALL
  { 33,	3,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
  { 34,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #34 = ICALL_BRANCH_FUNNEL
  { 35,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #35 = G_ADD
  { 36,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #36 = G_SUB
  { 37,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #37 = G_MUL
  { 38,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #38 = G_SDIV
  { 39,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #39 = G_UDIV
  { 40,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #40 = G_SREM
  { 41,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #41 = G_UREM
  { 42,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #42 = G_AND
  { 43,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #43 = G_OR
  { 44,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = G_XOR
  { 45,	1,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = G_IMPLICIT_DEF
  { 46,	1,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #46 = G_PHI
  { 47,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #47 = G_FRAME_INDEX
  { 48,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = G_GLOBAL_VALUE
  { 49,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #49 = G_EXTRACT
  { 50,	2,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #50 = G_UNMERGE_VALUES
  { 51,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = G_INSERT
  { 52,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #52 = G_MERGE_VALUES
  { 53,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = G_BUILD_VECTOR
  { 54,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #54 = G_BUILD_VECTOR_TRUNC
  { 55,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = G_CONCAT_VECTORS
  { 56,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #56 = G_PTRTOINT
  { 57,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #57 = G_INTTOPTR
  { 58,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #58 = G_BITCAST
  { 59,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #59 = G_INTRINSIC_TRUNC
  { 60,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #60 = G_INTRINSIC_ROUND
  { 61,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #61 = G_LOAD
  { 62,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #62 = G_SEXTLOAD
  { 63,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #63 = G_ZEXTLOAD
  { 64,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #64 = G_INDEXED_LOAD
  { 65,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #65 = G_INDEXED_SEXTLOAD
  { 66,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #66 = G_INDEXED_ZEXTLOAD
  { 67,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #67 = G_STORE
  { 68,	5,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #68 = G_INDEXED_STORE
  { 69,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #69 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
  { 70,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #70 = G_ATOMIC_CMPXCHG
  { 71,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #71 = G_ATOMICRMW_XCHG
  { 72,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #72 = G_ATOMICRMW_ADD
  { 73,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #73 = G_ATOMICRMW_SUB
  { 74,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #74 = G_ATOMICRMW_AND
  { 75,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #75 = G_ATOMICRMW_NAND
  { 76,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #76 = G_ATOMICRMW_OR
  { 77,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #77 = G_ATOMICRMW_XOR
  { 78,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #78 = G_ATOMICRMW_MAX
  { 79,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #79 = G_ATOMICRMW_MIN
  { 80,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #80 = G_ATOMICRMW_UMAX
  { 81,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #81 = G_ATOMICRMW_UMIN
  { 82,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #82 = G_ATOMICRMW_FADD
  { 83,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #83 = G_ATOMICRMW_FSUB
  { 84,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #84 = G_FENCE
  { 85,	2,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #85 = G_BRCOND
  { 86,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #86 = G_BRINDIRECT
  { 87,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #87 = G_INTRINSIC
  { 88,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #88 = G_INTRINSIC_W_SIDE_EFFECTS
  { 89,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #89 = G_ANYEXT
  { 90,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #90 = G_TRUNC
  { 91,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #91 = G_CONSTANT
  { 92,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #92 = G_FCONSTANT
  { 93,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #93 = G_VASTART
  { 94,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #94 = G_VAARG
  { 95,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #95 = G_SEXT
  { 96,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #96 = G_SEXT_INREG
  { 97,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #97 = G_ZEXT
  { 98,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #98 = G_SHL
  { 99,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #99 = G_LSHR
  { 100,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #100 = G_ASHR
  { 101,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #101 = G_ICMP
  { 102,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr },  // Inst #102 = G_FCMP
  { 103,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #103 = G_SELECT
  { 104,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #104 = G_UADDO
  { 105,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #105 = G_UADDE
  { 106,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #106 = G_USUBO
  { 107,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #107 = G_USUBE
  { 108,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #108 = G_SADDO
  { 109,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #109 = G_SADDE
  { 110,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #110 = G_SSUBO
  { 111,	5,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #111 = G_SSUBE
  { 112,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #112 = G_UMULO
  { 113,	4,	2,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #113 = G_SMULO
  { 114,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #114 = G_UMULH
  { 115,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #115 = G_SMULH
  { 116,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #116 = G_FADD
  { 117,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #117 = G_FSUB
  { 118,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #118 = G_FMUL
  { 119,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #119 = G_FMA
  { 120,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #120 = G_FMAD
  { 121,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #121 = G_FDIV
  { 122,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #122 = G_FREM
  { 123,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #123 = G_FPOW
  { 124,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #124 = G_FEXP
  { 125,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #125 = G_FEXP2
  { 126,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #126 = G_FLOG
  { 127,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #127 = G_FLOG2
  { 128,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #128 = G_FLOG10
  { 129,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #129 = G_FNEG
  { 130,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #130 = G_FPEXT
  { 131,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #131 = G_FPTRUNC
  { 132,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #132 = G_FPTOSI
  { 133,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #133 = G_FPTOUI
  { 134,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #134 = G_SITOFP
  { 135,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #135 = G_UITOFP
  { 136,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #136 = G_FABS
  { 137,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #137 = G_FCOPYSIGN
  { 138,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #138 = G_FCANONICALIZE
  { 139,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #139 = G_FMINNUM
  { 140,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #140 = G_FMAXNUM
  { 141,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #141 = G_FMINNUM_IEEE
  { 142,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #142 = G_FMAXNUM_IEEE
  { 143,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #143 = G_FMINIMUM
  { 144,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #144 = G_FMAXIMUM
  { 145,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #145 = G_GEP
  { 146,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #146 = G_PTR_MASK
  { 147,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #147 = G_SMIN
  { 148,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #148 = G_SMAX
  { 149,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #149 = G_UMIN
  { 150,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #150 = G_UMAX
  { 151,	1,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #151 = G_BR
  { 152,	3,	0,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #152 = G_BRJT
  { 153,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #153 = G_INSERT_VECTOR_ELT
  { 154,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #154 = G_EXTRACT_VECTOR_ELT
  { 155,	4,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #155 = G_SHUFFLE_VECTOR
  { 156,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #156 = G_CTTZ
  { 157,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #157 = G_CTTZ_ZERO_UNDEF
  { 158,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #158 = G_CTLZ
  { 159,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #159 = G_CTLZ_ZERO_UNDEF
  { 160,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #160 = G_CTPOP
  { 161,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #161 = G_BSWAP
  { 162,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #162 = G_BITREVERSE
  { 163,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #163 = G_FCEIL
  { 164,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #164 = G_FCOS
  { 165,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #165 = G_FSIN
  { 166,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #166 = G_FSQRT
  { 167,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #167 = G_FFLOOR
  { 168,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #168 = G_FRINT
  { 169,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #169 = G_FNEARBYINT
  { 170,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #170 = G_ADDRSPACE_CAST
  { 171,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #171 = G_BLOCK_ADDR
  { 172,	2,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #172 = G_JUMP_TABLE
  { 173,	3,	1,	0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #173 = G_DYN_STACKALLOC
  { 174,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #174 = CATCHRET
  { 175,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #175 = CATCHRET_S
  { 176,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #176 = CLEANUPRET
  { 177,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::EHScopeReturn)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #177 = CLEANUPRET_S
  { 178,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #178 = COMPILER_FENCE
  { 179,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #179 = COMPILER_FENCE_S
  { 180,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #180 = RETHROW_IN_CATCH
  { 181,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #181 = RETHROW_IN_CATCH_S
  { 182,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #182 = ABS_F32
  { 183,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #183 = ABS_F32_S
  { 184,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #184 = ABS_F64
  { 185,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #185 = ABS_F64_S
  { 186,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #186 = ABS_v2f64
  { 187,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #187 = ABS_v2f64_S
  { 188,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #188 = ABS_v4f32
  { 189,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #189 = ABS_v4f32_S
  { 190,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #190 = ADD_F32
  { 191,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #191 = ADD_F32_S
  { 192,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #192 = ADD_F64
  { 193,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #193 = ADD_F64_S
  { 194,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #194 = ADD_I32
  { 195,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #195 = ADD_I32_S
  { 196,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #196 = ADD_I64
  { 197,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #197 = ADD_I64_S
  { 198,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #198 = ADD_SAT_S_v16i8
  { 199,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #199 = ADD_SAT_S_v16i8_S
  { 200,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #200 = ADD_SAT_S_v8i16
  { 201,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #201 = ADD_SAT_S_v8i16_S
  { 202,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #202 = ADD_SAT_U_v16i8
  { 203,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #203 = ADD_SAT_U_v16i8_S
  { 204,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #204 = ADD_SAT_U_v8i16
  { 205,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #205 = ADD_SAT_U_v8i16_S
  { 206,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #206 = ADD_v16i8
  { 207,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #207 = ADD_v16i8_S
  { 208,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #208 = ADD_v2f64
  { 209,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #209 = ADD_v2f64_S
  { 210,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #210 = ADD_v2i64
  { 211,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #211 = ADD_v2i64_S
  { 212,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #212 = ADD_v4f32
  { 213,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #213 = ADD_v4f32_S
  { 214,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #214 = ADD_v4i32
  { 215,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #215 = ADD_v4i32_S
  { 216,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #216 = ADD_v8i16
  { 217,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #217 = ADD_v8i16_S
  { 218,	2,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #218 = ADJCALLSTACKDOWN
  { 219,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #219 = ADJCALLSTACKDOWN_S
  { 220,	2,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #220 = ADJCALLSTACKUP
  { 221,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #221 = ADJCALLSTACKUP_S
  { 222,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #222 = ALLTRUE_v16i8
  { 223,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #223 = ALLTRUE_v16i8_S
  { 224,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #224 = ALLTRUE_v2i64
  { 225,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #225 = ALLTRUE_v2i64_S
  { 226,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #226 = ALLTRUE_v4i32
  { 227,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #227 = ALLTRUE_v4i32_S
  { 228,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #228 = ALLTRUE_v8i16
  { 229,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #229 = ALLTRUE_v8i16_S
  { 230,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #230 = ANDNOT_v16i8
  { 231,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #231 = ANDNOT_v16i8_S
  { 232,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #232 = ANDNOT_v2i64
  { 233,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #233 = ANDNOT_v2i64_S
  { 234,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #234 = ANDNOT_v4i32
  { 235,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #235 = ANDNOT_v4i32_S
  { 236,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #236 = ANDNOT_v8i16
  { 237,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #237 = ANDNOT_v8i16_S
  { 238,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #238 = AND_I32
  { 239,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #239 = AND_I32_S
  { 240,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #240 = AND_I64
  { 241,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #241 = AND_I64_S
  { 242,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #242 = AND_v16i8
  { 243,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #243 = AND_v16i8_S
  { 244,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #244 = AND_v2i64
  { 245,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #245 = AND_v2i64_S
  { 246,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #246 = AND_v4i32
  { 247,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #247 = AND_v4i32_S
  { 248,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #248 = AND_v8i16
  { 249,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #249 = AND_v8i16_S
  { 250,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #250 = ANYTRUE_v16i8
  { 251,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #251 = ANYTRUE_v16i8_S
  { 252,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #252 = ANYTRUE_v2i64
  { 253,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #253 = ANYTRUE_v2i64_S
  { 254,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #254 = ANYTRUE_v4i32
  { 255,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #255 = ANYTRUE_v4i32_S
  { 256,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #256 = ANYTRUE_v8i16
  { 257,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #257 = ANYTRUE_v8i16_S
  { 258,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #258 = ARGUMENT_exnref
  { 259,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #259 = ARGUMENT_exnref_S
  { 260,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #260 = ARGUMENT_f32
  { 261,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #261 = ARGUMENT_f32_S
  { 262,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #262 = ARGUMENT_f64
  { 263,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #263 = ARGUMENT_f64_S
  { 264,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #264 = ARGUMENT_i32
  { 265,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #265 = ARGUMENT_i32_S
  { 266,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #266 = ARGUMENT_i64
  { 267,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #267 = ARGUMENT_i64_S
  { 268,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #268 = ARGUMENT_v16i8
  { 269,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #269 = ARGUMENT_v16i8_S
  { 270,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #270 = ARGUMENT_v2f64
  { 271,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #271 = ARGUMENT_v2f64_S
  { 272,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #272 = ARGUMENT_v2i64
  { 273,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #273 = ARGUMENT_v2i64_S
  { 274,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #274 = ARGUMENT_v4f32
  { 275,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #275 = ARGUMENT_v4f32_S
  { 276,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #276 = ARGUMENT_v4i32
  { 277,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #277 = ARGUMENT_v4i32_S
  { 278,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #278 = ARGUMENT_v8i16
  { 279,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #279 = ARGUMENT_v8i16_S
  { 280,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #280 = ATOMIC_FENCE
  { 281,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #281 = ATOMIC_FENCE_S
  { 282,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #282 = ATOMIC_LOAD16_U_I32
  { 283,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #283 = ATOMIC_LOAD16_U_I32_S
  { 284,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #284 = ATOMIC_LOAD16_U_I64
  { 285,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #285 = ATOMIC_LOAD16_U_I64_S
  { 286,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #286 = ATOMIC_LOAD32_U_I64
  { 287,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #287 = ATOMIC_LOAD32_U_I64_S
  { 288,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #288 = ATOMIC_LOAD8_U_I32
  { 289,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #289 = ATOMIC_LOAD8_U_I32_S
  { 290,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #290 = ATOMIC_LOAD8_U_I64
  { 291,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #291 = ATOMIC_LOAD8_U_I64_S
  { 292,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #292 = ATOMIC_LOAD_I32
  { 293,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #293 = ATOMIC_LOAD_I32_S
  { 294,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #294 = ATOMIC_LOAD_I64
  { 295,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #295 = ATOMIC_LOAD_I64_S
  { 296,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #296 = ATOMIC_NOTIFY
  { 297,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #297 = ATOMIC_NOTIFY_S
  { 298,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #298 = ATOMIC_RMW16_U_ADD_I32
  { 299,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #299 = ATOMIC_RMW16_U_ADD_I32_S
  { 300,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #300 = ATOMIC_RMW16_U_ADD_I64
  { 301,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #301 = ATOMIC_RMW16_U_ADD_I64_S
  { 302,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #302 = ATOMIC_RMW16_U_AND_I32
  { 303,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #303 = ATOMIC_RMW16_U_AND_I32_S
  { 304,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #304 = ATOMIC_RMW16_U_AND_I64
  { 305,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #305 = ATOMIC_RMW16_U_AND_I64_S
  { 306,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #306 = ATOMIC_RMW16_U_CMPXCHG_I32
  { 307,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #307 = ATOMIC_RMW16_U_CMPXCHG_I32_S
  { 308,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #308 = ATOMIC_RMW16_U_CMPXCHG_I64
  { 309,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #309 = ATOMIC_RMW16_U_CMPXCHG_I64_S
  { 310,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #310 = ATOMIC_RMW16_U_OR_I32
  { 311,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #311 = ATOMIC_RMW16_U_OR_I32_S
  { 312,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #312 = ATOMIC_RMW16_U_OR_I64
  { 313,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #313 = ATOMIC_RMW16_U_OR_I64_S
  { 314,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #314 = ATOMIC_RMW16_U_SUB_I32
  { 315,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #315 = ATOMIC_RMW16_U_SUB_I32_S
  { 316,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #316 = ATOMIC_RMW16_U_SUB_I64
  { 317,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #317 = ATOMIC_RMW16_U_SUB_I64_S
  { 318,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #318 = ATOMIC_RMW16_U_XCHG_I32
  { 319,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #319 = ATOMIC_RMW16_U_XCHG_I32_S
  { 320,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #320 = ATOMIC_RMW16_U_XCHG_I64
  { 321,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #321 = ATOMIC_RMW16_U_XCHG_I64_S
  { 322,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #322 = ATOMIC_RMW16_U_XOR_I32
  { 323,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #323 = ATOMIC_RMW16_U_XOR_I32_S
  { 324,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #324 = ATOMIC_RMW16_U_XOR_I64
  { 325,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #325 = ATOMIC_RMW16_U_XOR_I64_S
  { 326,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #326 = ATOMIC_RMW32_U_ADD_I64
  { 327,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #327 = ATOMIC_RMW32_U_ADD_I64_S
  { 328,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #328 = ATOMIC_RMW32_U_AND_I64
  { 329,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #329 = ATOMIC_RMW32_U_AND_I64_S
  { 330,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #330 = ATOMIC_RMW32_U_CMPXCHG_I64
  { 331,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #331 = ATOMIC_RMW32_U_CMPXCHG_I64_S
  { 332,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #332 = ATOMIC_RMW32_U_OR_I64
  { 333,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #333 = ATOMIC_RMW32_U_OR_I64_S
  { 334,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #334 = ATOMIC_RMW32_U_SUB_I64
  { 335,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #335 = ATOMIC_RMW32_U_SUB_I64_S
  { 336,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #336 = ATOMIC_RMW32_U_XCHG_I64
  { 337,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #337 = ATOMIC_RMW32_U_XCHG_I64_S
  { 338,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #338 = ATOMIC_RMW32_U_XOR_I64
  { 339,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #339 = ATOMIC_RMW32_U_XOR_I64_S
  { 340,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #340 = ATOMIC_RMW8_U_ADD_I32
  { 341,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #341 = ATOMIC_RMW8_U_ADD_I32_S
  { 342,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #342 = ATOMIC_RMW8_U_ADD_I64
  { 343,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #343 = ATOMIC_RMW8_U_ADD_I64_S
  { 344,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #344 = ATOMIC_RMW8_U_AND_I32
  { 345,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #345 = ATOMIC_RMW8_U_AND_I32_S
  { 346,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #346 = ATOMIC_RMW8_U_AND_I64
  { 347,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #347 = ATOMIC_RMW8_U_AND_I64_S
  { 348,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #348 = ATOMIC_RMW8_U_CMPXCHG_I32
  { 349,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #349 = ATOMIC_RMW8_U_CMPXCHG_I32_S
  { 350,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #350 = ATOMIC_RMW8_U_CMPXCHG_I64
  { 351,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #351 = ATOMIC_RMW8_U_CMPXCHG_I64_S
  { 352,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #352 = ATOMIC_RMW8_U_OR_I32
  { 353,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #353 = ATOMIC_RMW8_U_OR_I32_S
  { 354,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #354 = ATOMIC_RMW8_U_OR_I64
  { 355,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #355 = ATOMIC_RMW8_U_OR_I64_S
  { 356,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #356 = ATOMIC_RMW8_U_SUB_I32
  { 357,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #357 = ATOMIC_RMW8_U_SUB_I32_S
  { 358,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #358 = ATOMIC_RMW8_U_SUB_I64
  { 359,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #359 = ATOMIC_RMW8_U_SUB_I64_S
  { 360,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #360 = ATOMIC_RMW8_U_XCHG_I32
  { 361,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #361 = ATOMIC_RMW8_U_XCHG_I32_S
  { 362,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #362 = ATOMIC_RMW8_U_XCHG_I64
  { 363,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #363 = ATOMIC_RMW8_U_XCHG_I64_S
  { 364,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #364 = ATOMIC_RMW8_U_XOR_I32
  { 365,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #365 = ATOMIC_RMW8_U_XOR_I32_S
  { 366,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #366 = ATOMIC_RMW8_U_XOR_I64
  { 367,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #367 = ATOMIC_RMW8_U_XOR_I64_S
  { 368,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #368 = ATOMIC_RMW_ADD_I32
  { 369,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #369 = ATOMIC_RMW_ADD_I32_S
  { 370,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #370 = ATOMIC_RMW_ADD_I64
  { 371,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #371 = ATOMIC_RMW_ADD_I64_S
  { 372,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #372 = ATOMIC_RMW_AND_I32
  { 373,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #373 = ATOMIC_RMW_AND_I32_S
  { 374,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #374 = ATOMIC_RMW_AND_I64
  { 375,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #375 = ATOMIC_RMW_AND_I64_S
  { 376,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo57, -1 ,nullptr },  // Inst #376 = ATOMIC_RMW_CMPXCHG_I32
  { 377,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #377 = ATOMIC_RMW_CMPXCHG_I32_S
  { 378,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr },  // Inst #378 = ATOMIC_RMW_CMPXCHG_I64
  { 379,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #379 = ATOMIC_RMW_CMPXCHG_I64_S
  { 380,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #380 = ATOMIC_RMW_OR_I32
  { 381,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #381 = ATOMIC_RMW_OR_I32_S
  { 382,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #382 = ATOMIC_RMW_OR_I64
  { 383,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #383 = ATOMIC_RMW_OR_I64_S
  { 384,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #384 = ATOMIC_RMW_SUB_I32
  { 385,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #385 = ATOMIC_RMW_SUB_I32_S
  { 386,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #386 = ATOMIC_RMW_SUB_I64
  { 387,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #387 = ATOMIC_RMW_SUB_I64_S
  { 388,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #388 = ATOMIC_RMW_XCHG_I32
  { 389,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #389 = ATOMIC_RMW_XCHG_I32_S
  { 390,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #390 = ATOMIC_RMW_XCHG_I64
  { 391,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #391 = ATOMIC_RMW_XCHG_I64_S
  { 392,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr },  // Inst #392 = ATOMIC_RMW_XOR_I32
  { 393,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #393 = ATOMIC_RMW_XOR_I32_S
  { 394,	5,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo56, -1 ,nullptr },  // Inst #394 = ATOMIC_RMW_XOR_I64
  { 395,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #395 = ATOMIC_RMW_XOR_I64_S
  { 396,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #396 = ATOMIC_STORE16_I32
  { 397,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #397 = ATOMIC_STORE16_I32_S
  { 398,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #398 = ATOMIC_STORE16_I64
  { 399,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #399 = ATOMIC_STORE16_I64_S
  { 400,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #400 = ATOMIC_STORE32_I64
  { 401,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #401 = ATOMIC_STORE32_I64_S
  { 402,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #402 = ATOMIC_STORE8_I32
  { 403,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #403 = ATOMIC_STORE8_I32_S
  { 404,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #404 = ATOMIC_STORE8_I64
  { 405,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #405 = ATOMIC_STORE8_I64_S
  { 406,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #406 = ATOMIC_STORE_I32
  { 407,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #407 = ATOMIC_STORE_I32_S
  { 408,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #408 = ATOMIC_STORE_I64
  { 409,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #409 = ATOMIC_STORE_I64_S
  { 410,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #410 = ATOMIC_WAIT_I32
  { 411,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #411 = ATOMIC_WAIT_I32_S
  { 412,	6,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo62, -1 ,nullptr },  // Inst #412 = ATOMIC_WAIT_I64
  { 413,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #413 = ATOMIC_WAIT_I64_S
  { 414,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #414 = BITSELECT_v16i8
  { 415,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #415 = BITSELECT_v16i8_S
  { 416,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #416 = BITSELECT_v2f64
  { 417,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #417 = BITSELECT_v2f64_S
  { 418,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #418 = BITSELECT_v2i64
  { 419,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #419 = BITSELECT_v2i64_S
  { 420,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #420 = BITSELECT_v4f32
  { 421,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #421 = BITSELECT_v4f32_S
  { 422,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #422 = BITSELECT_v4i32
  { 423,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #423 = BITSELECT_v4i32_S
  { 424,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #424 = BITSELECT_v8i16
  { 425,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #425 = BITSELECT_v8i16_S
  { 426,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #426 = BLOCK
  { 427,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #427 = BLOCK_S
  { 428,	1,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #428 = BR
  { 429,	2,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #429 = BR_IF
  { 430,	1,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #430 = BR_IF_S
  { 431,	3,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #431 = BR_ON_EXN
  { 432,	2,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo68, -1 ,nullptr },  // Inst #432 = BR_ON_EXN_S
  { 433,	1,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #433 = BR_S
  { 434,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #434 = BR_TABLE_I32
  { 435,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr },  // Inst #435 = BR_TABLE_I32_S
  { 436,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #436 = BR_TABLE_I64
  { 437,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo70, -1 ,nullptr },  // Inst #437 = BR_TABLE_I64_S
  { 438,	2,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #438 = BR_UNLESS
  { 439,	1,	0,	0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo65, -1 ,nullptr },  // Inst #439 = BR_UNLESS_S
  { 440,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #440 = CALL_INDIRECT_VOID
  { 441,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #441 = CALL_INDIRECT_VOID_S
  { 442,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo73, -1 ,nullptr },  // Inst #442 = CALL_INDIRECT_exnref
  { 443,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #443 = CALL_INDIRECT_exnref_S
  { 444,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #444 = CALL_INDIRECT_f32
  { 445,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #445 = CALL_INDIRECT_f32_S
  { 446,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo75, -1 ,nullptr },  // Inst #446 = CALL_INDIRECT_f64
  { 447,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #447 = CALL_INDIRECT_f64_S
  { 448,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo76, -1 ,nullptr },  // Inst #448 = CALL_INDIRECT_i32
  { 449,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #449 = CALL_INDIRECT_i32_S
  { 450,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo77, -1 ,nullptr },  // Inst #450 = CALL_INDIRECT_i64
  { 451,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #451 = CALL_INDIRECT_i64_S
  { 452,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #452 = CALL_INDIRECT_v16i8
  { 453,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #453 = CALL_INDIRECT_v16i8_S
  { 454,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #454 = CALL_INDIRECT_v2f64
  { 455,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #455 = CALL_INDIRECT_v2f64_S
  { 456,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #456 = CALL_INDIRECT_v2i64
  { 457,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #457 = CALL_INDIRECT_v2i64_S
  { 458,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #458 = CALL_INDIRECT_v4f32
  { 459,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #459 = CALL_INDIRECT_v4f32_S
  { 460,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #460 = CALL_INDIRECT_v4i32
  { 461,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #461 = CALL_INDIRECT_v4i32_S
  { 462,	3,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #462 = CALL_INDIRECT_v8i16
  { 463,	2,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #463 = CALL_INDIRECT_v8i16_S
  { 464,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #464 = CALL_VOID
  { 465,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #465 = CALL_VOID_S
  { 466,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #466 = CALL_exnref
  { 467,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #467 = CALL_exnref_S
  { 468,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #468 = CALL_f32
  { 469,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #469 = CALL_f32_S
  { 470,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo82, -1 ,nullptr },  // Inst #470 = CALL_f64
  { 471,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #471 = CALL_f64_S
  { 472,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo83, -1 ,nullptr },  // Inst #472 = CALL_i32
  { 473,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #473 = CALL_i32_S
  { 474,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo84, -1 ,nullptr },  // Inst #474 = CALL_i64
  { 475,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #475 = CALL_i64_S
  { 476,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #476 = CALL_v16i8
  { 477,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #477 = CALL_v16i8_S
  { 478,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #478 = CALL_v2f64
  { 479,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #479 = CALL_v2f64_S
  { 480,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #480 = CALL_v2i64
  { 481,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #481 = CALL_v2i64_S
  { 482,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #482 = CALL_v4f32
  { 483,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #483 = CALL_v4f32_S
  { 484,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #484 = CALL_v4i32
  { 485,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #485 = CALL_v4i32_S
  { 486,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #486 = CALL_v8i16
  { 487,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #487 = CALL_v8i16_S
  { 488,	1,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #488 = CATCH
  { 489,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #489 = CATCH_S
  { 490,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #490 = CEIL_F32
  { 491,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #491 = CEIL_F32_S
  { 492,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #492 = CEIL_F64
  { 493,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #493 = CEIL_F64_S
  { 494,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #494 = CLZ_I32
  { 495,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #495 = CLZ_I32_S
  { 496,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #496 = CLZ_I64
  { 497,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #497 = CLZ_I64_S
  { 498,	2,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo89, -1 ,nullptr },  // Inst #498 = CONST_F32
  { 499,	1,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr },  // Inst #499 = CONST_F32_S
  { 500,	2,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr },  // Inst #500 = CONST_F64
  { 501,	1,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr },  // Inst #501 = CONST_F64_S
  { 502,	2,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #502 = CONST_I32
  { 503,	1,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #503 = CONST_I32_S
  { 504,	2,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #504 = CONST_I64
  { 505,	1,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr },  // Inst #505 = CONST_I64_S
  { 506,	17,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr },  // Inst #506 = CONST_V128_v16i8
  { 507,	16,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr },  // Inst #507 = CONST_V128_v16i8_S
  { 508,	3,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo99, -1 ,nullptr },  // Inst #508 = CONST_V128_v2f64
  { 509,	2,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo100, -1 ,nullptr },  // Inst #509 = CONST_V128_v2f64_S
  { 510,	3,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo101, -1 ,nullptr },  // Inst #510 = CONST_V128_v2i64
  { 511,	2,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr },  // Inst #511 = CONST_V128_v2i64_S
  { 512,	5,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr },  // Inst #512 = CONST_V128_v4f32
  { 513,	4,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #513 = CONST_V128_v4f32_S
  { 514,	5,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo105, -1 ,nullptr },  // Inst #514 = CONST_V128_v4i32
  { 515,	4,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr },  // Inst #515 = CONST_V128_v4i32_S
  { 516,	9,	1,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr },  // Inst #516 = CONST_V128_v8i16
  { 517,	8,	0,	0,	0,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr },  // Inst #517 = CONST_V128_v8i16_S
  { 518,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #518 = COPYSIGN_F32
  { 519,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #519 = COPYSIGN_F32_S
  { 520,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #520 = COPYSIGN_F64
  { 521,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #521 = COPYSIGN_F64_S
  { 522,	2,	1,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #522 = COPY_EXNREF
  { 523,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #523 = COPY_EXNREF_S
  { 524,	2,	1,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #524 = COPY_F32
  { 525,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #525 = COPY_F32_S
  { 526,	2,	1,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #526 = COPY_F64
  { 527,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #527 = COPY_F64_S
  { 528,	2,	1,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #528 = COPY_I32
  { 529,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #529 = COPY_I32_S
  { 530,	2,	1,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #530 = COPY_I64
  { 531,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #531 = COPY_I64_S
  { 532,	2,	1,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #532 = COPY_V128
  { 533,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #533 = COPY_V128_S
  { 534,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #534 = CTZ_I32
  { 535,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #535 = CTZ_I32_S
  { 536,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #536 = CTZ_I64
  { 537,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #537 = CTZ_I64_S
  { 538,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #538 = DATA_DROP
  { 539,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #539 = DATA_DROP_S
  { 540,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #540 = DIV_F32
  { 541,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #541 = DIV_F32_S
  { 542,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #542 = DIV_F64
  { 543,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #543 = DIV_F64_S
  { 544,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #544 = DIV_S_I32
  { 545,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #545 = DIV_S_I32_S
  { 546,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #546 = DIV_S_I64
  { 547,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #547 = DIV_S_I64_S
  { 548,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #548 = DIV_U_I32
  { 549,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #549 = DIV_U_I32_S
  { 550,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #550 = DIV_U_I64
  { 551,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #551 = DIV_U_I64_S
  { 552,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #552 = DIV_v2f64
  { 553,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #553 = DIV_v2f64_S
  { 554,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #554 = DIV_v4f32
  { 555,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #555 = DIV_v4f32_S
  { 556,	1,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #556 = DROP_EXNREF
  { 557,	0,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #557 = DROP_EXNREF_S
  { 558,	1,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr },  // Inst #558 = DROP_F32
  { 559,	0,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #559 = DROP_F32_S
  { 560,	1,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr },  // Inst #560 = DROP_F64
  { 561,	0,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #561 = DROP_F64_S
  { 562,	1,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #562 = DROP_I32
  { 563,	0,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #563 = DROP_I32_S
  { 564,	1,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr },  // Inst #564 = DROP_I64
  { 565,	0,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #565 = DROP_I64_S
  { 566,	1,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr },  // Inst #566 = DROP_V128
  { 567,	0,	0,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #567 = DROP_V128_S
  { 568,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #568 = ELSE
  { 569,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #569 = ELSE_S
  { 570,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #570 = END
  { 571,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #571 = END_BLOCK
  { 572,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #572 = END_BLOCK_S
  { 573,	0,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #573 = END_FUNCTION
  { 574,	0,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #574 = END_FUNCTION_S
  { 575,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #575 = END_IF
  { 576,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #576 = END_IF_S
  { 577,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #577 = END_LOOP
  { 578,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #578 = END_LOOP_S
  { 579,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #579 = END_S
  { 580,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #580 = END_TRY
  { 581,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, nullptr, -1 ,nullptr },  // Inst #581 = END_TRY_S
  { 582,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #582 = EQZ_I32
  { 583,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #583 = EQZ_I32_S
  { 584,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr },  // Inst #584 = EQZ_I64
  { 585,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #585 = EQZ_I64_S
  { 586,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr },  // Inst #586 = EQ_F32
  { 587,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #587 = EQ_F32_S
  { 588,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #588 = EQ_F64
  { 589,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #589 = EQ_F64_S
  { 590,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #590 = EQ_I32
  { 591,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #591 = EQ_I32_S
  { 592,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #592 = EQ_I64
  { 593,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #593 = EQ_I64_S
  { 594,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #594 = EQ_v16i8
  { 595,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #595 = EQ_v16i8_S
  { 596,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #596 = EQ_v2f64
  { 597,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #597 = EQ_v2f64_S
  { 598,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #598 = EQ_v4f32
  { 599,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #599 = EQ_v4f32_S
  { 600,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #600 = EQ_v4i32
  { 601,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #601 = EQ_v4i32_S
  { 602,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #602 = EQ_v8i16
  { 603,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #603 = EQ_v8i16_S
  { 604,	1,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #604 = EXTRACT_EXCEPTION_I32
  { 605,	1,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #605 = EXTRACT_EXCEPTION_I32_S
  { 606,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr },  // Inst #606 = EXTRACT_LANE_v16i8_s
  { 607,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #607 = EXTRACT_LANE_v16i8_s_S
  { 608,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr },  // Inst #608 = EXTRACT_LANE_v16i8_u
  { 609,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #609 = EXTRACT_LANE_v16i8_u_S
  { 610,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo119, -1 ,nullptr },  // Inst #610 = EXTRACT_LANE_v2f64
  { 611,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #611 = EXTRACT_LANE_v2f64_S
  { 612,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo120, -1 ,nullptr },  // Inst #612 = EXTRACT_LANE_v2i64
  { 613,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #613 = EXTRACT_LANE_v2i64_S
  { 614,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo121, -1 ,nullptr },  // Inst #614 = EXTRACT_LANE_v4f32
  { 615,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #615 = EXTRACT_LANE_v4f32_S
  { 616,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr },  // Inst #616 = EXTRACT_LANE_v4i32
  { 617,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #617 = EXTRACT_LANE_v4i32_S
  { 618,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr },  // Inst #618 = EXTRACT_LANE_v8i16_s
  { 619,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #619 = EXTRACT_LANE_v8i16_s_S
  { 620,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo117, -1 ,nullptr },  // Inst #620 = EXTRACT_LANE_v8i16_u
  { 621,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #621 = EXTRACT_LANE_v8i16_u_S
  { 622,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #622 = F32_CONVERT_S_I32
  { 623,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #623 = F32_CONVERT_S_I32_S
  { 624,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo123, -1 ,nullptr },  // Inst #624 = F32_CONVERT_S_I64
  { 625,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #625 = F32_CONVERT_S_I64_S
  { 626,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #626 = F32_CONVERT_U_I32
  { 627,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #627 = F32_CONVERT_U_I32_S
  { 628,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo123, -1 ,nullptr },  // Inst #628 = F32_CONVERT_U_I64
  { 629,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #629 = F32_CONVERT_U_I64_S
  { 630,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo124, -1 ,nullptr },  // Inst #630 = F32_DEMOTE_F64
  { 631,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #631 = F32_DEMOTE_F64_S
  { 632,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #632 = F32_REINTERPRET_I32
  { 633,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #633 = F32_REINTERPRET_I32_S
  { 634,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo125, -1 ,nullptr },  // Inst #634 = F64_CONVERT_S_I32
  { 635,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #635 = F64_CONVERT_S_I32_S
  { 636,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #636 = F64_CONVERT_S_I64
  { 637,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #637 = F64_CONVERT_S_I64_S
  { 638,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo125, -1 ,nullptr },  // Inst #638 = F64_CONVERT_U_I32
  { 639,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #639 = F64_CONVERT_U_I32_S
  { 640,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #640 = F64_CONVERT_U_I64
  { 641,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #641 = F64_CONVERT_U_I64_S
  { 642,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #642 = F64_PROMOTE_F32
  { 643,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #643 = F64_PROMOTE_F32_S
  { 644,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #644 = F64_REINTERPRET_I64
  { 645,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #645 = F64_REINTERPRET_I64_S
  { 646,	0,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #646 = FALLTHROUGH_RETURN
  { 647,	0,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #647 = FALLTHROUGH_RETURN_S
  { 648,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #648 = FLOOR_F32
  { 649,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #649 = FLOOR_F32_S
  { 650,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #650 = FLOOR_F64
  { 651,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #651 = FLOOR_F64_S
  { 652,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #652 = FP_TO_SINT_I32_F32
  { 653,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #653 = FP_TO_SINT_I32_F32_S
  { 654,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo129, -1 ,nullptr },  // Inst #654 = FP_TO_SINT_I32_F64
  { 655,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #655 = FP_TO_SINT_I32_F64_S
  { 656,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr },  // Inst #656 = FP_TO_SINT_I64_F32
  { 657,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #657 = FP_TO_SINT_I64_F32_S
  { 658,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #658 = FP_TO_SINT_I64_F64
  { 659,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #659 = FP_TO_SINT_I64_F64_S
  { 660,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #660 = FP_TO_UINT_I32_F32
  { 661,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #661 = FP_TO_UINT_I32_F32_S
  { 662,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo129, -1 ,nullptr },  // Inst #662 = FP_TO_UINT_I32_F64
  { 663,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #663 = FP_TO_UINT_I32_F64_S
  { 664,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr },  // Inst #664 = FP_TO_UINT_I64_F32
  { 665,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #665 = FP_TO_UINT_I64_F32_S
  { 666,	2,	1,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #666 = FP_TO_UINT_I64_F64
  { 667,	0,	0,	0,	0,	0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #667 = FP_TO_UINT_I64_F64_S
  { 668,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr },  // Inst #668 = GE_F32
  { 669,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #669 = GE_F32_S
  { 670,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #670 = GE_F64
  { 671,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #671 = GE_F64_S
  { 672,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #672 = GE_S_I32
  { 673,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #673 = GE_S_I32_S
  { 674,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #674 = GE_S_I64
  { 675,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #675 = GE_S_I64_S
  { 676,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #676 = GE_S_v16i8
  { 677,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #677 = GE_S_v16i8_S
  { 678,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #678 = GE_S_v4i32
  { 679,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #679 = GE_S_v4i32_S
  { 680,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #680 = GE_S_v8i16
  { 681,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #681 = GE_S_v8i16_S
  { 682,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #682 = GE_U_I32
  { 683,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #683 = GE_U_I32_S
  { 684,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #684 = GE_U_I64
  { 685,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #685 = GE_U_I64_S
  { 686,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #686 = GE_U_v16i8
  { 687,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #687 = GE_U_v16i8_S
  { 688,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #688 = GE_U_v4i32
  { 689,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #689 = GE_U_v4i32_S
  { 690,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #690 = GE_U_v8i16
  { 691,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #691 = GE_U_v8i16_S
  { 692,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #692 = GE_v2f64
  { 693,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #693 = GE_v2f64_S
  { 694,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #694 = GE_v4f32
  { 695,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #695 = GE_v4f32_S
  { 696,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo132, -1 ,nullptr },  // Inst #696 = GLOBAL_GET_EXNREF
  { 697,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #697 = GLOBAL_GET_EXNREF_S
  { 698,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo134, -1 ,nullptr },  // Inst #698 = GLOBAL_GET_F32
  { 699,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #699 = GLOBAL_GET_F32_S
  { 700,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo135, -1 ,nullptr },  // Inst #700 = GLOBAL_GET_F64
  { 701,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #701 = GLOBAL_GET_F64_S
  { 702,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo136, -1 ,nullptr },  // Inst #702 = GLOBAL_GET_I32
  { 703,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #703 = GLOBAL_GET_I32_S
  { 704,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo137, -1 ,nullptr },  // Inst #704 = GLOBAL_GET_I64
  { 705,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #705 = GLOBAL_GET_I64_S
  { 706,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo138, -1 ,nullptr },  // Inst #706 = GLOBAL_GET_V128
  { 707,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #707 = GLOBAL_GET_V128_S
  { 708,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo139, -1 ,nullptr },  // Inst #708 = GLOBAL_SET_EXNREF
  { 709,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #709 = GLOBAL_SET_EXNREF_S
  { 710,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo140, -1 ,nullptr },  // Inst #710 = GLOBAL_SET_F32
  { 711,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #711 = GLOBAL_SET_F32_S
  { 712,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo141, -1 ,nullptr },  // Inst #712 = GLOBAL_SET_F64
  { 713,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #713 = GLOBAL_SET_F64_S
  { 714,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr },  // Inst #714 = GLOBAL_SET_I32
  { 715,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #715 = GLOBAL_SET_I32_S
  { 716,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo143, -1 ,nullptr },  // Inst #716 = GLOBAL_SET_I64
  { 717,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #717 = GLOBAL_SET_I64_S
  { 718,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr },  // Inst #718 = GLOBAL_SET_V128
  { 719,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo133, -1 ,nullptr },  // Inst #719 = GLOBAL_SET_V128_S
  { 720,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr },  // Inst #720 = GT_F32
  { 721,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #721 = GT_F32_S
  { 722,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #722 = GT_F64
  { 723,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #723 = GT_F64_S
  { 724,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #724 = GT_S_I32
  { 725,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #725 = GT_S_I32_S
  { 726,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #726 = GT_S_I64
  { 727,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #727 = GT_S_I64_S
  { 728,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #728 = GT_S_v16i8
  { 729,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #729 = GT_S_v16i8_S
  { 730,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #730 = GT_S_v4i32
  { 731,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #731 = GT_S_v4i32_S
  { 732,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #732 = GT_S_v8i16
  { 733,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #733 = GT_S_v8i16_S
  { 734,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #734 = GT_U_I32
  { 735,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #735 = GT_U_I32_S
  { 736,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #736 = GT_U_I64
  { 737,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #737 = GT_U_I64_S
  { 738,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #738 = GT_U_v16i8
  { 739,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #739 = GT_U_v16i8_S
  { 740,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #740 = GT_U_v4i32
  { 741,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #741 = GT_U_v4i32_S
  { 742,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #742 = GT_U_v8i16
  { 743,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #743 = GT_U_v8i16_S
  { 744,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #744 = GT_v2f64
  { 745,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #745 = GT_v2f64_S
  { 746,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #746 = GT_v4f32
  { 747,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #747 = GT_v4f32_S
  { 748,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #748 = I32_EXTEND16_S_I32
  { 749,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #749 = I32_EXTEND16_S_I32_S
  { 750,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #750 = I32_EXTEND8_S_I32
  { 751,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #751 = I32_EXTEND8_S_I32_S
  { 752,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #752 = I32_REINTERPRET_F32
  { 753,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #753 = I32_REINTERPRET_F32_S
  { 754,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #754 = I32_TRUNC_S_F32
  { 755,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #755 = I32_TRUNC_S_F32_S
  { 756,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo129, -1 ,nullptr },  // Inst #756 = I32_TRUNC_S_F64
  { 757,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #757 = I32_TRUNC_S_F64_S
  { 758,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #758 = I32_TRUNC_S_SAT_F32
  { 759,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #759 = I32_TRUNC_S_SAT_F32_S
  { 760,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo129, -1 ,nullptr },  // Inst #760 = I32_TRUNC_S_SAT_F64
  { 761,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #761 = I32_TRUNC_S_SAT_F64_S
  { 762,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #762 = I32_TRUNC_U_F32
  { 763,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #763 = I32_TRUNC_U_F32_S
  { 764,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo129, -1 ,nullptr },  // Inst #764 = I32_TRUNC_U_F64
  { 765,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #765 = I32_TRUNC_U_F64_S
  { 766,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #766 = I32_TRUNC_U_SAT_F32
  { 767,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #767 = I32_TRUNC_U_SAT_F32_S
  { 768,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo129, -1 ,nullptr },  // Inst #768 = I32_TRUNC_U_SAT_F64
  { 769,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #769 = I32_TRUNC_U_SAT_F64_S
  { 770,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo113, -1 ,nullptr },  // Inst #770 = I32_WRAP_I64
  { 771,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #771 = I32_WRAP_I64_S
  { 772,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #772 = I64_EXTEND16_S_I64
  { 773,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #773 = I64_EXTEND16_S_I64_S
  { 774,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #774 = I64_EXTEND32_S_I64
  { 775,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #775 = I64_EXTEND32_S_I64_S
  { 776,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #776 = I64_EXTEND8_S_I64
  { 777,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #777 = I64_EXTEND8_S_I64_S
  { 778,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr },  // Inst #778 = I64_EXTEND_S_I32
  { 779,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #779 = I64_EXTEND_S_I32_S
  { 780,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr },  // Inst #780 = I64_EXTEND_U_I32
  { 781,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #781 = I64_EXTEND_U_I32_S
  { 782,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #782 = I64_REINTERPRET_F64
  { 783,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #783 = I64_REINTERPRET_F64_S
  { 784,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr },  // Inst #784 = I64_TRUNC_S_F32
  { 785,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #785 = I64_TRUNC_S_F32_S
  { 786,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #786 = I64_TRUNC_S_F64
  { 787,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #787 = I64_TRUNC_S_F64_S
  { 788,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr },  // Inst #788 = I64_TRUNC_S_SAT_F32
  { 789,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #789 = I64_TRUNC_S_SAT_F32_S
  { 790,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #790 = I64_TRUNC_S_SAT_F64
  { 791,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #791 = I64_TRUNC_S_SAT_F64_S
  { 792,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr },  // Inst #792 = I64_TRUNC_U_F32
  { 793,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #793 = I64_TRUNC_U_F32_S
  { 794,	2,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #794 = I64_TRUNC_U_F64
  { 795,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #795 = I64_TRUNC_U_F64_S
  { 796,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo130, -1 ,nullptr },  // Inst #796 = I64_TRUNC_U_SAT_F32
  { 797,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #797 = I64_TRUNC_U_SAT_F32_S
  { 798,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #798 = I64_TRUNC_U_SAT_F64
  { 799,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #799 = I64_TRUNC_U_SAT_F64_S
  { 800,	2,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo146, -1 ,nullptr },  // Inst #800 = IF
  { 801,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #801 = IF_S
  { 802,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr },  // Inst #802 = LE_F32
  { 803,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #803 = LE_F32_S
  { 804,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #804 = LE_F64
  { 805,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #805 = LE_F64_S
  { 806,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #806 = LE_S_I32
  { 807,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #807 = LE_S_I32_S
  { 808,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #808 = LE_S_I64
  { 809,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #809 = LE_S_I64_S
  { 810,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #810 = LE_S_v16i8
  { 811,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #811 = LE_S_v16i8_S
  { 812,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #812 = LE_S_v4i32
  { 813,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #813 = LE_S_v4i32_S
  { 814,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #814 = LE_S_v8i16
  { 815,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #815 = LE_S_v8i16_S
  { 816,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #816 = LE_U_I32
  { 817,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #817 = LE_U_I32_S
  { 818,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #818 = LE_U_I64
  { 819,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #819 = LE_U_I64_S
  { 820,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #820 = LE_U_v16i8
  { 821,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #821 = LE_U_v16i8_S
  { 822,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #822 = LE_U_v4i32
  { 823,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #823 = LE_U_v4i32_S
  { 824,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #824 = LE_U_v8i16
  { 825,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #825 = LE_U_v8i16_S
  { 826,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #826 = LE_v2f64
  { 827,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #827 = LE_v2f64_S
  { 828,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #828 = LE_v4f32
  { 829,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #829 = LE_v4f32_S
  { 830,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #830 = LOAD16_S_I32
  { 831,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #831 = LOAD16_S_I32_S
  { 832,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #832 = LOAD16_S_I64
  { 833,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #833 = LOAD16_S_I64_S
  { 834,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #834 = LOAD16_U_I32
  { 835,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #835 = LOAD16_U_I32_S
  { 836,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #836 = LOAD16_U_I64
  { 837,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #837 = LOAD16_U_I64_S
  { 838,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #838 = LOAD32_S_I64
  { 839,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #839 = LOAD32_S_I64_S
  { 840,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #840 = LOAD32_U_I64
  { 841,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #841 = LOAD32_U_I64_S
  { 842,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #842 = LOAD8_S_I32
  { 843,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #843 = LOAD8_S_I32_S
  { 844,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #844 = LOAD8_S_I64
  { 845,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #845 = LOAD8_S_I64_S
  { 846,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #846 = LOAD8_U_I32
  { 847,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #847 = LOAD8_U_I32_S
  { 848,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #848 = LOAD8_U_I64
  { 849,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #849 = LOAD8_U_I64_S
  { 850,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #850 = LOAD_EXTEND_S_v2i64
  { 851,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #851 = LOAD_EXTEND_S_v2i64_S
  { 852,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #852 = LOAD_EXTEND_S_v4i32
  { 853,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #853 = LOAD_EXTEND_S_v4i32_S
  { 854,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #854 = LOAD_EXTEND_S_v8i16
  { 855,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #855 = LOAD_EXTEND_S_v8i16_S
  { 856,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #856 = LOAD_EXTEND_U_v2i64
  { 857,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #857 = LOAD_EXTEND_U_v2i64_S
  { 858,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #858 = LOAD_EXTEND_U_v4i32
  { 859,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #859 = LOAD_EXTEND_U_v4i32_S
  { 860,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #860 = LOAD_EXTEND_U_v8i16
  { 861,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #861 = LOAD_EXTEND_U_v8i16_S
  { 862,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo148, -1 ,nullptr },  // Inst #862 = LOAD_F32
  { 863,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #863 = LOAD_F32_S
  { 864,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr },  // Inst #864 = LOAD_F64
  { 865,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #865 = LOAD_F64_S
  { 866,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo52, -1 ,nullptr },  // Inst #866 = LOAD_I32
  { 867,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #867 = LOAD_I32_S
  { 868,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo54, -1 ,nullptr },  // Inst #868 = LOAD_I64
  { 869,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #869 = LOAD_I64_S
  { 870,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #870 = LOAD_SPLAT_v16x8
  { 871,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #871 = LOAD_SPLAT_v16x8_S
  { 872,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #872 = LOAD_SPLAT_v32x4
  { 873,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #873 = LOAD_SPLAT_v32x4_S
  { 874,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #874 = LOAD_SPLAT_v64x2
  { 875,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #875 = LOAD_SPLAT_v64x2_S
  { 876,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #876 = LOAD_SPLAT_v8x16
  { 877,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #877 = LOAD_SPLAT_v8x16_S
  { 878,	4,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo147, -1 ,nullptr },  // Inst #878 = LOAD_V128
  { 879,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #879 = LOAD_V128_S
  { 880,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo150, -1 ,nullptr },  // Inst #880 = LOCAL_GET_EXNREF
  { 881,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #881 = LOCAL_GET_EXNREF_S
  { 882,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo152, -1 ,nullptr },  // Inst #882 = LOCAL_GET_F32
  { 883,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #883 = LOCAL_GET_F32_S
  { 884,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo153, -1 ,nullptr },  // Inst #884 = LOCAL_GET_F64
  { 885,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #885 = LOCAL_GET_F64_S
  { 886,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo154, -1 ,nullptr },  // Inst #886 = LOCAL_GET_I32
  { 887,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #887 = LOCAL_GET_I32_S
  { 888,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo155, -1 ,nullptr },  // Inst #888 = LOCAL_GET_I64
  { 889,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #889 = LOCAL_GET_I64_S
  { 890,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo156, -1 ,nullptr },  // Inst #890 = LOCAL_GET_V128
  { 891,	1,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #891 = LOCAL_GET_V128_S
  { 892,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo157, -1 ,nullptr },  // Inst #892 = LOCAL_SET_EXNREF
  { 893,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #893 = LOCAL_SET_EXNREF_S
  { 894,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo158, -1 ,nullptr },  // Inst #894 = LOCAL_SET_F32
  { 895,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #895 = LOCAL_SET_F32_S
  { 896,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo159, -1 ,nullptr },  // Inst #896 = LOCAL_SET_F64
  { 897,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #897 = LOCAL_SET_F64_S
  { 898,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo160, -1 ,nullptr },  // Inst #898 = LOCAL_SET_I32
  { 899,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #899 = LOCAL_SET_I32_S
  { 900,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr },  // Inst #900 = LOCAL_SET_I64
  { 901,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #901 = LOCAL_SET_I64_S
  { 902,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr },  // Inst #902 = LOCAL_SET_V128
  { 903,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #903 = LOCAL_SET_V128_S
  { 904,	3,	1,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr },  // Inst #904 = LOCAL_TEE_EXNREF
  { 905,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #905 = LOCAL_TEE_EXNREF_S
  { 906,	3,	1,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo164, -1 ,nullptr },  // Inst #906 = LOCAL_TEE_F32
  { 907,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #907 = LOCAL_TEE_F32_S
  { 908,	3,	1,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo165, -1 ,nullptr },  // Inst #908 = LOCAL_TEE_F64
  { 909,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #909 = LOCAL_TEE_F64_S
  { 910,	3,	1,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo166, -1 ,nullptr },  // Inst #910 = LOCAL_TEE_I32
  { 911,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #911 = LOCAL_TEE_I32_S
  { 912,	3,	1,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo167, -1 ,nullptr },  // Inst #912 = LOCAL_TEE_I64
  { 913,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #913 = LOCAL_TEE_I64_S
  { 914,	3,	1,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo168, -1 ,nullptr },  // Inst #914 = LOCAL_TEE_V128
  { 915,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #915 = LOCAL_TEE_V128_S
  { 916,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #916 = LOOP
  { 917,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #917 = LOOP_S
  { 918,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr },  // Inst #918 = LT_F32
  { 919,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #919 = LT_F32_S
  { 920,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #920 = LT_F64
  { 921,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #921 = LT_F64_S
  { 922,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #922 = LT_S_I32
  { 923,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #923 = LT_S_I32_S
  { 924,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #924 = LT_S_I64
  { 925,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #925 = LT_S_I64_S
  { 926,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #926 = LT_S_v16i8
  { 927,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #927 = LT_S_v16i8_S
  { 928,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #928 = LT_S_v4i32
  { 929,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #929 = LT_S_v4i32_S
  { 930,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #930 = LT_S_v8i16
  { 931,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #931 = LT_S_v8i16_S
  { 932,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #932 = LT_U_I32
  { 933,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #933 = LT_U_I32_S
  { 934,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #934 = LT_U_I64
  { 935,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #935 = LT_U_I64_S
  { 936,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #936 = LT_U_v16i8
  { 937,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #937 = LT_U_v16i8_S
  { 938,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #938 = LT_U_v4i32
  { 939,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #939 = LT_U_v4i32_S
  { 940,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #940 = LT_U_v8i16
  { 941,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #941 = LT_U_v8i16_S
  { 942,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #942 = LT_v2f64
  { 943,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #943 = LT_v2f64_S
  { 944,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #944 = LT_v4f32
  { 945,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #945 = LT_v4f32_S
  { 946,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #946 = MAX_F32
  { 947,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #947 = MAX_F32_S
  { 948,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #948 = MAX_F64
  { 949,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #949 = MAX_F64_S
  { 950,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #950 = MAX_v2f64
  { 951,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #951 = MAX_v2f64_S
  { 952,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #952 = MAX_v4f32
  { 953,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #953 = MAX_v4f32_S
  { 954,	5,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr },  // Inst #954 = MEMORY_COPY
  { 955,	2,	0,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #955 = MEMORY_COPY_S
  { 956,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo171, -1 ,nullptr },  // Inst #956 = MEMORY_FILL
  { 957,	1,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #957 = MEMORY_FILL_S
  { 958,	3,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #958 = MEMORY_GROW_I32
  { 959,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #959 = MEMORY_GROW_I32_S
  { 960,	5,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo169, -1 ,nullptr },  // Inst #960 = MEMORY_INIT
  { 961,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #961 = MEMORY_INIT_S
  { 962,	2,	1,	0,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo49, -1 ,nullptr },  // Inst #962 = MEMORY_SIZE_I32
  { 963,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo3, -1 ,nullptr },  // Inst #963 = MEMORY_SIZE_I32_S
  { 964,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #964 = MIN_F32
  { 965,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #965 = MIN_F32_S
  { 966,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #966 = MIN_F64
  { 967,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #967 = MIN_F64_S
  { 968,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #968 = MIN_v2f64
  { 969,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #969 = MIN_v2f64_S
  { 970,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #970 = MIN_v4f32
  { 971,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #971 = MIN_v4f32_S
  { 972,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #972 = MUL_F32
  { 973,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #973 = MUL_F32_S
  { 974,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #974 = MUL_F64
  { 975,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #975 = MUL_F64_S
  { 976,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #976 = MUL_I32
  { 977,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #977 = MUL_I32_S
  { 978,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #978 = MUL_I64
  { 979,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #979 = MUL_I64_S
  { 980,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #980 = MUL_v16i8
  { 981,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #981 = MUL_v16i8_S
  { 982,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #982 = MUL_v2f64
  { 983,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #983 = MUL_v2f64_S
  { 984,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #984 = MUL_v4f32
  { 985,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #985 = MUL_v4f32_S
  { 986,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #986 = MUL_v4i32
  { 987,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #987 = MUL_v4i32_S
  { 988,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #988 = MUL_v8i16
  { 989,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #989 = MUL_v8i16_S
  { 990,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #990 = NARROW_S_v16i8
  { 991,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #991 = NARROW_S_v16i8_S
  { 992,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #992 = NARROW_S_v8i16
  { 993,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #993 = NARROW_S_v8i16_S
  { 994,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #994 = NARROW_U_v16i8
  { 995,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #995 = NARROW_U_v16i8_S
  { 996,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #996 = NARROW_U_v8i16
  { 997,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #997 = NARROW_U_v8i16_S
  { 998,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #998 = NEAREST_F32
  { 999,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #999 = NEAREST_F32_S
  { 1000,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #1000 = NEAREST_F64
  { 1001,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1001 = NEAREST_F64_S
  { 1002,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #1002 = NEG_F32
  { 1003,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1003 = NEG_F32_S
  { 1004,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #1004 = NEG_F64
  { 1005,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1005 = NEG_F64_S
  { 1006,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1006 = NEG_v16i8
  { 1007,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1007 = NEG_v16i8_S
  { 1008,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1008 = NEG_v2f64
  { 1009,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1009 = NEG_v2f64_S
  { 1010,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1010 = NEG_v2i64
  { 1011,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1011 = NEG_v2i64_S
  { 1012,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1012 = NEG_v4f32
  { 1013,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1013 = NEG_v4f32_S
  { 1014,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1014 = NEG_v4i32
  { 1015,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1015 = NEG_v4i32_S
  { 1016,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1016 = NEG_v8i16
  { 1017,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1017 = NEG_v8i16_S
  { 1018,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo114, -1 ,nullptr },  // Inst #1018 = NE_F32
  { 1019,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1019 = NE_F32_S
  { 1020,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr },  // Inst #1020 = NE_F64
  { 1021,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1021 = NE_F64_S
  { 1022,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1022 = NE_I32
  { 1023,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1023 = NE_I32_S
  { 1024,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo116, -1 ,nullptr },  // Inst #1024 = NE_I64
  { 1025,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1025 = NE_I64_S
  { 1026,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1026 = NE_v16i8
  { 1027,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1027 = NE_v16i8_S
  { 1028,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1028 = NE_v2f64
  { 1029,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1029 = NE_v2f64_S
  { 1030,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1030 = NE_v4f32
  { 1031,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1031 = NE_v4f32_S
  { 1032,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1032 = NE_v4i32
  { 1033,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1033 = NE_v4i32_S
  { 1034,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1034 = NE_v8i16
  { 1035,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1035 = NE_v8i16_S
  { 1036,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1036 = NOP
  { 1037,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1037 = NOP_S
  { 1038,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1038 = NOT_v16i8
  { 1039,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1039 = NOT_v16i8_S
  { 1040,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1040 = NOT_v2i64
  { 1041,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1041 = NOT_v2i64_S
  { 1042,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1042 = NOT_v4i32
  { 1043,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1043 = NOT_v4i32_S
  { 1044,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1044 = NOT_v8i16
  { 1045,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1045 = NOT_v8i16_S
  { 1046,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1046 = OR_I32
  { 1047,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1047 = OR_I32_S
  { 1048,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1048 = OR_I64
  { 1049,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1049 = OR_I64_S
  { 1050,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1050 = OR_v16i8
  { 1051,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1051 = OR_v16i8_S
  { 1052,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1052 = OR_v2i64
  { 1053,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1053 = OR_v2i64_S
  { 1054,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1054 = OR_v4i32
  { 1055,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1055 = OR_v4i32_S
  { 1056,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1056 = OR_v8i16
  { 1057,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1057 = OR_v8i16_S
  { 1058,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1058 = PCALL_INDIRECT_VOID
  { 1059,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1059 = PCALL_INDIRECT_VOID_S
  { 1060,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo173, -1 ,nullptr },  // Inst #1060 = PCALL_INDIRECT_exnref
  { 1061,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1061 = PCALL_INDIRECT_exnref_S
  { 1062,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #1062 = PCALL_INDIRECT_f32
  { 1063,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1063 = PCALL_INDIRECT_f32_S
  { 1064,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo125, -1 ,nullptr },  // Inst #1064 = PCALL_INDIRECT_f64
  { 1065,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1065 = PCALL_INDIRECT_f64_S
  { 1066,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #1066 = PCALL_INDIRECT_i32
  { 1067,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1067 = PCALL_INDIRECT_i32_S
  { 1068,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo145, -1 ,nullptr },  // Inst #1068 = PCALL_INDIRECT_i64
  { 1069,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1069 = PCALL_INDIRECT_i64_S
  { 1070,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1070 = PCALL_INDIRECT_v16i8
  { 1071,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1071 = PCALL_INDIRECT_v16i8_S
  { 1072,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1072 = PCALL_INDIRECT_v2f64
  { 1073,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1073 = PCALL_INDIRECT_v2f64_S
  { 1074,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1074 = PCALL_INDIRECT_v2i64
  { 1075,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1075 = PCALL_INDIRECT_v2i64_S
  { 1076,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1076 = PCALL_INDIRECT_v4f32
  { 1077,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1077 = PCALL_INDIRECT_v4f32_S
  { 1078,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1078 = PCALL_INDIRECT_v4i32
  { 1079,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1079 = PCALL_INDIRECT_v4i32_S
  { 1080,	2,	1,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1080 = PCALL_INDIRECT_v8i16
  { 1081,	1,	0,	0,	0,	0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1081 = PCALL_INDIRECT_v8i16_S
  { 1082,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #1082 = POPCNT_I32
  { 1083,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1083 = POPCNT_I32_S
  { 1084,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #1084 = POPCNT_I64
  { 1085,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1085 = POPCNT_I64_S
  { 1086,	1,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1086 = PRET_CALL_INDIRECT
  { 1087,	1,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo69, -1 ,nullptr },  // Inst #1087 = PRET_CALL_INDIRECT_S
  { 1088,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #1088 = QFMA_v2f64
  { 1089,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1089 = QFMA_v2f64_S
  { 1090,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #1090 = QFMA_v4f32
  { 1091,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1091 = QFMA_v4f32_S
  { 1092,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #1092 = QFMS_v2f64
  { 1093,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1093 = QFMS_v2f64_S
  { 1094,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo63, -1 ,nullptr },  // Inst #1094 = QFMS_v4f32
  { 1095,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1095 = QFMS_v4f32_S
  { 1096,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1096 = REM_S_I32
  { 1097,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1097 = REM_S_I32_S
  { 1098,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1098 = REM_S_I64
  { 1099,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1099 = REM_S_I64_S
  { 1100,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1100 = REM_U_I32
  { 1101,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1101 = REM_U_I32_S
  { 1102,	3,	1,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1102 = REM_U_I64
  { 1103,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1103 = REM_U_I64_S
  { 1104,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1104 = REPLACE_LANE_v16i8
  { 1105,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #1105 = REPLACE_LANE_v16i8_S
  { 1106,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo176, -1 ,nullptr },  // Inst #1106 = REPLACE_LANE_v2f64
  { 1107,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #1107 = REPLACE_LANE_v2f64_S
  { 1108,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo177, -1 ,nullptr },  // Inst #1108 = REPLACE_LANE_v2i64
  { 1109,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #1109 = REPLACE_LANE_v2i64_S
  { 1110,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1110 = REPLACE_LANE_v4f32
  { 1111,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #1111 = REPLACE_LANE_v4f32_S
  { 1112,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1112 = REPLACE_LANE_v4i32
  { 1113,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #1113 = REPLACE_LANE_v4i32_S
  { 1114,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1114 = REPLACE_LANE_v8i16
  { 1115,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo118, -1 ,nullptr },  // Inst #1115 = REPLACE_LANE_v8i16_S
  { 1116,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #1116 = RETHROW
  { 1117,	0,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1117 = RETHROW_S
  { 1118,	0,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1118 = RETURN
  { 1119,	0,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1119 = RETURN_S
  { 1120,	1,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #1120 = RET_CALL
  { 1121,	2,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #1121 = RET_CALL_INDIRECT
  { 1122,	2,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #1122 = RET_CALL_INDIRECT_S
  { 1123,	1,	0,	0,	0,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #1123 = RET_CALL_S
  { 1124,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1124 = ROTL_I32
  { 1125,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1125 = ROTL_I32_S
  { 1126,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1126 = ROTL_I64
  { 1127,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1127 = ROTL_I64_S
  { 1128,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1128 = ROTR_I32
  { 1129,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1129 = ROTR_I32_S
  { 1130,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1130 = ROTR_I64
  { 1131,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1131 = ROTR_I64_S
  { 1132,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo179, -1 ,nullptr },  // Inst #1132 = SELECT_EXNREF
  { 1133,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1133 = SELECT_EXNREF_S
  { 1134,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr },  // Inst #1134 = SELECT_F32
  { 1135,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1135 = SELECT_F32_S
  { 1136,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo181, -1 ,nullptr },  // Inst #1136 = SELECT_F64
  { 1137,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1137 = SELECT_F64_S
  { 1138,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo182, -1 ,nullptr },  // Inst #1138 = SELECT_I32
  { 1139,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1139 = SELECT_I32_S
  { 1140,	4,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo183, -1 ,nullptr },  // Inst #1140 = SELECT_I64
  { 1141,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1141 = SELECT_I64_S
  { 1142,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1142 = SHL_I32
  { 1143,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1143 = SHL_I32_S
  { 1144,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1144 = SHL_I64
  { 1145,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1145 = SHL_I64_S
  { 1146,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1146 = SHL_v16i8
  { 1147,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1147 = SHL_v16i8_S
  { 1148,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1148 = SHL_v2i64
  { 1149,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1149 = SHL_v2i64_S
  { 1150,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1150 = SHL_v4i32
  { 1151,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1151 = SHL_v4i32_S
  { 1152,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1152 = SHL_v8i16
  { 1153,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1153 = SHL_v8i16_S
  { 1154,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1154 = SHR_S_I32
  { 1155,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1155 = SHR_S_I32_S
  { 1156,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1156 = SHR_S_I64
  { 1157,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1157 = SHR_S_I64_S
  { 1158,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1158 = SHR_S_v16i8
  { 1159,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1159 = SHR_S_v16i8_S
  { 1160,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1160 = SHR_S_v2i64
  { 1161,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1161 = SHR_S_v2i64_S
  { 1162,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1162 = SHR_S_v4i32
  { 1163,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1163 = SHR_S_v4i32_S
  { 1164,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1164 = SHR_S_v8i16
  { 1165,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1165 = SHR_S_v8i16_S
  { 1166,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1166 = SHR_U_I32
  { 1167,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1167 = SHR_U_I32_S
  { 1168,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1168 = SHR_U_I64
  { 1169,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1169 = SHR_U_I64_S
  { 1170,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1170 = SHR_U_v16i8
  { 1171,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1171 = SHR_U_v16i8_S
  { 1172,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1172 = SHR_U_v2i64
  { 1173,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1173 = SHR_U_v2i64_S
  { 1174,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1174 = SHR_U_v4i32
  { 1175,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1175 = SHR_U_v4i32_S
  { 1176,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo184, -1 ,nullptr },  // Inst #1176 = SHR_U_v8i16
  { 1177,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1177 = SHR_U_v8i16_S
  { 1178,	19,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo185, -1 ,nullptr },  // Inst #1178 = SHUFFLE
  { 1179,	16,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo98, -1 ,nullptr },  // Inst #1179 = SHUFFLE_S
  { 1180,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1180 = SPLAT_v16i8
  { 1181,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1181 = SPLAT_v16i8_S
  { 1182,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo186, -1 ,nullptr },  // Inst #1182 = SPLAT_v2f64
  { 1183,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1183 = SPLAT_v2f64_S
  { 1184,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo187, -1 ,nullptr },  // Inst #1184 = SPLAT_v2i64
  { 1185,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1185 = SPLAT_v2i64_S
  { 1186,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo188, -1 ,nullptr },  // Inst #1186 = SPLAT_v4f32
  { 1187,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1187 = SPLAT_v4f32_S
  { 1188,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1188 = SPLAT_v4i32
  { 1189,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1189 = SPLAT_v4i32_S
  { 1190,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo174, -1 ,nullptr },  // Inst #1190 = SPLAT_v8i16
  { 1191,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1191 = SPLAT_v8i16_S
  { 1192,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #1192 = SQRT_F32
  { 1193,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1193 = SQRT_F32_S
  { 1194,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #1194 = SQRT_F64
  { 1195,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1195 = SQRT_F64_S
  { 1196,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1196 = SQRT_v2f64
  { 1197,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1197 = SQRT_v2f64_S
  { 1198,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1198 = SQRT_v4f32
  { 1199,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1199 = SQRT_v4f32_S
  { 1200,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #1200 = STORE16_I32
  { 1201,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1201 = STORE16_I32_S
  { 1202,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #1202 = STORE16_I64
  { 1203,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1203 = STORE16_I64_S
  { 1204,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #1204 = STORE32_I64
  { 1205,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1205 = STORE32_I64_S
  { 1206,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #1206 = STORE8_I32
  { 1207,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1207 = STORE8_I32_S
  { 1208,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #1208 = STORE8_I64
  { 1209,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1209 = STORE8_I64_S
  { 1210,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo189, -1 ,nullptr },  // Inst #1210 = STORE_F32
  { 1211,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1211 = STORE_F32_S
  { 1212,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr },  // Inst #1212 = STORE_F64
  { 1213,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1213 = STORE_F64_S
  { 1214,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #1214 = STORE_I32
  { 1215,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1215 = STORE_I32_S
  { 1216,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #1216 = STORE_I64
  { 1217,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1217 = STORE_I64_S
  { 1218,	4,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo191, -1 ,nullptr },  // Inst #1218 = STORE_V128
  { 1219,	2,	0,	0,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #1219 = STORE_V128_S
  { 1220,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #1220 = SUB_F32
  { 1221,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1221 = SUB_F32_S
  { 1222,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #1222 = SUB_F64
  { 1223,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1223 = SUB_F64_S
  { 1224,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1224 = SUB_I32
  { 1225,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1225 = SUB_I32_S
  { 1226,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1226 = SUB_I64
  { 1227,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1227 = SUB_I64_S
  { 1228,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1228 = SUB_SAT_S_v16i8
  { 1229,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1229 = SUB_SAT_S_v16i8_S
  { 1230,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1230 = SUB_SAT_S_v8i16
  { 1231,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1231 = SUB_SAT_S_v8i16_S
  { 1232,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1232 = SUB_SAT_U_v16i8
  { 1233,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1233 = SUB_SAT_U_v16i8_S
  { 1234,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1234 = SUB_SAT_U_v8i16
  { 1235,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1235 = SUB_SAT_U_v8i16_S
  { 1236,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1236 = SUB_v16i8
  { 1237,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1237 = SUB_v16i8_S
  { 1238,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1238 = SUB_v2f64
  { 1239,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1239 = SUB_v2f64_S
  { 1240,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1240 = SUB_v2i64
  { 1241,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1241 = SUB_v2i64_S
  { 1242,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1242 = SUB_v4f32
  { 1243,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1243 = SUB_v4f32_S
  { 1244,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1244 = SUB_v4i32
  { 1245,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1245 = SUB_v4i32_S
  { 1246,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1246 = SUB_v8i16
  { 1247,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1247 = SUB_v8i16_S
  { 1248,	3,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1248 = SWIZZLE
  { 1249,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1249 = SWIZZLE_S
  { 1250,	3,	2,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo192, -1 ,nullptr },  // Inst #1250 = TEE_EXNREF
  { 1251,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1251 = TEE_EXNREF_S
  { 1252,	3,	2,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #1252 = TEE_F32
  { 1253,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1253 = TEE_F32_S
  { 1254,	3,	2,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #1254 = TEE_F64
  { 1255,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1255 = TEE_F64_S
  { 1256,	3,	2,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1256 = TEE_I32
  { 1257,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1257 = TEE_I32_S
  { 1258,	3,	2,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1258 = TEE_I64
  { 1259,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1259 = TEE_I64_S
  { 1260,	3,	2,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1260 = TEE_V128
  { 1261,	0,	0,	0,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1261 = TEE_V128_S
  { 1262,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr },  // Inst #1262 = THROW
  { 1263,	1,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr },  // Inst #1263 = THROW_S
  { 1264,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #1264 = TRUNC_F32
  { 1265,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1265 = TRUNC_F32_S
  { 1266,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #1266 = TRUNC_F64
  { 1267,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1267 = TRUNC_F64_S
  { 1268,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #1268 = TRY
  { 1269,	1,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, ImplicitList3, OperandInfo64, -1 ,nullptr },  // Inst #1269 = TRY_S
  { 1270,	0,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1270 = UNREACHABLE
  { 1271,	0,	0,	0,	0,	0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1271 = UNREACHABLE_S
  { 1272,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr },  // Inst #1272 = XOR_I32
  { 1273,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1273 = XOR_I32_S
  { 1274,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #1274 = XOR_I64
  { 1275,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1275 = XOR_I64_S
  { 1276,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1276 = XOR_v16i8
  { 1277,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1277 = XOR_v16i8_S
  { 1278,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1278 = XOR_v2i64
  { 1279,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1279 = XOR_v2i64_S
  { 1280,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1280 = XOR_v4i32
  { 1281,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1281 = XOR_v4i32_S
  { 1282,	3,	1,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #1282 = XOR_v8i16
  { 1283,	0,	0,	0,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1283 = XOR_v8i16_S
  { 1284,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1284 = fp_to_sint_v2i64_v2f64
  { 1285,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1285 = fp_to_sint_v2i64_v2f64_S
  { 1286,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1286 = fp_to_sint_v4i32_v4f32
  { 1287,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1287 = fp_to_sint_v4i32_v4f32_S
  { 1288,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1288 = fp_to_uint_v2i64_v2f64
  { 1289,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1289 = fp_to_uint_v2i64_v2f64_S
  { 1290,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1290 = fp_to_uint_v4i32_v4f32
  { 1291,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1291 = fp_to_uint_v4i32_v4f32_S
  { 1292,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1292 = int_wasm_widen_high_signed_v4i32_v8i16
  { 1293,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1293 = int_wasm_widen_high_signed_v4i32_v8i16_S
  { 1294,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1294 = int_wasm_widen_high_signed_v8i16_v16i8
  { 1295,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1295 = int_wasm_widen_high_signed_v8i16_v16i8_S
  { 1296,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1296 = int_wasm_widen_high_unsigned_v4i32_v8i16
  { 1297,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1297 = int_wasm_widen_high_unsigned_v4i32_v8i16_S
  { 1298,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1298 = int_wasm_widen_high_unsigned_v8i16_v16i8
  { 1299,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1299 = int_wasm_widen_high_unsigned_v8i16_v16i8_S
  { 1300,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1300 = int_wasm_widen_low_signed_v4i32_v8i16
  { 1301,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1301 = int_wasm_widen_low_signed_v4i32_v8i16_S
  { 1302,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1302 = int_wasm_widen_low_signed_v8i16_v16i8
  { 1303,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1303 = int_wasm_widen_low_signed_v8i16_v16i8_S
  { 1304,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1304 = int_wasm_widen_low_unsigned_v4i32_v8i16
  { 1305,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1305 = int_wasm_widen_low_unsigned_v4i32_v8i16_S
  { 1306,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1306 = int_wasm_widen_low_unsigned_v8i16_v16i8
  { 1307,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1307 = int_wasm_widen_low_unsigned_v8i16_v16i8_S
  { 1308,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1308 = sint_to_fp_v2f64_v2i64
  { 1309,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1309 = sint_to_fp_v2f64_v2i64_S
  { 1310,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1310 = sint_to_fp_v4f32_v4i32
  { 1311,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1311 = sint_to_fp_v4f32_v4i32_S
  { 1312,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1312 = uint_to_fp_v2f64_v2i64
  { 1313,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1313 = uint_to_fp_v2f64_v2i64_S
  { 1314,	2,	1,	0,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #1314 = uint_to_fp_v4f32_v4i32
  { 1315,	0,	0,	0,	0,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #1315 = uint_to_fp_v4f32_v4i32_S
};

extern const char WebAssemblyInstrNameData[] = {
  /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
  /* 9 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '3', '2', 0,
  /* 28 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '3', '2', 0,
  /* 47 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '3', '2', 0,
  /* 66 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '3', '2', 0,
  /* 85 */ 'S', 'U', 'B', '_', 'F', '3', '2', 0,
  /* 93 */ 'T', 'R', 'U', 'N', 'C', '_', 'F', '3', '2', 0,
  /* 103 */ 'L', 'O', 'A', 'D', '_', 'F', '3', '2', 0,
  /* 112 */ 'A', 'D', 'D', '_', 'F', '3', '2', 0,
  /* 120 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'F', '3', '2', 0,
  /* 134 */ 'G', 'E', '_', 'F', '3', '2', 0,
  /* 141 */ 'L', 'E', '_', 'F', '3', '2', 0,
  /* 148 */ 'N', 'E', '_', 'F', '3', '2', 0,
  /* 155 */ 'S', 'T', 'O', 'R', 'E', '_', 'F', '3', '2', 0,
  /* 165 */ 'F', '6', '4', '_', 'P', 'R', 'O', 'M', 'O', 'T', 'E', '_', 'F', '3', '2', 0,
  /* 181 */ 'N', 'E', 'G', '_', 'F', '3', '2', 0,
  /* 189 */ 'C', 'E', 'I', 'L', '_', 'F', '3', '2', 0,
  /* 198 */ 'M', 'U', 'L', '_', 'F', '3', '2', 0,
  /* 206 */ 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', '_', 'F', '3', '2', 0,
  /* 219 */ 'M', 'I', 'N', '_', 'F', '3', '2', 0,
  /* 227 */ 'D', 'R', 'O', 'P', '_', 'F', '3', '2', 0,
  /* 236 */ 'E', 'Q', '_', 'F', '3', '2', 0,
  /* 243 */ 'F', 'L', 'O', 'O', 'R', '_', 'F', '3', '2', 0,
  /* 253 */ 'A', 'B', 'S', '_', 'F', '3', '2', 0,
  /* 261 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '3', '2', 0,
  /* 277 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '3', '2', 0,
  /* 293 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '3', '2', 0,
  /* 313 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '3', '2', 0,
  /* 333 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '3', '2', 0,
  /* 353 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '3', '2', 0,
  /* 373 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '3', '2', 0,
  /* 384 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '3', '2', 0,
  /* 399 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '3', '2', 0,
  /* 413 */ 'I', '3', '2', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'F', '3', '2', 0,
  /* 433 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '3', '2', 0,
  /* 448 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '3', '2', 0,
  /* 462 */ 'G', 'T', '_', 'F', '3', '2', 0,
  /* 469 */ 'L', 'T', '_', 'F', '3', '2', 0,
  /* 476 */ 'S', 'Q', 'R', 'T', '_', 'F', '3', '2', 0,
  /* 485 */ 'N', 'E', 'A', 'R', 'E', 'S', 'T', '_', 'F', '3', '2', 0,
  /* 497 */ 'C', 'O', 'N', 'S', 'T', '_', 'F', '3', '2', 0,
  /* 507 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '3', '2', 0,
  /* 523 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '3', '2', 0,
  /* 539 */ 'D', 'I', 'V', '_', 'F', '3', '2', 0,
  /* 547 */ 'M', 'A', 'X', '_', 'F', '3', '2', 0,
  /* 555 */ 'C', 'O', 'P', 'Y', '_', 'F', '3', '2', 0,
  /* 564 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '1', '6', '_', 'I', '3', '2', 0,
  /* 583 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '8', '_', 'I', '3', '2', 0,
  /* 601 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0,
  /* 624 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0,
  /* 646 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0,
  /* 665 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'I', '3', '2', 0,
  /* 681 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0,
  /* 704 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0,
  /* 726 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0,
  /* 745 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
  /* 768 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
  /* 790 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
  /* 809 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'I', '3', '2', 0,
  /* 823 */ 'B', 'R', '_', 'T', 'A', 'B', 'L', 'E', '_', 'I', '3', '2', 0,
  /* 836 */ 'N', 'E', '_', 'I', '3', '2', 0,
  /* 843 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '_', 'I', '3', '2', 0,
  /* 860 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'S', 'I', 'Z', 'E', '_', 'I', '3', '2', 0,
  /* 876 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', 0,
  /* 903 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', 0,
  /* 929 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', 0,
  /* 952 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', 0,
  /* 976 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', 0,
  /* 999 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', 0,
  /* 1019 */ 'S', 'H', 'L', '_', 'I', '3', '2', 0,
  /* 1027 */ 'R', 'O', 'T', 'L', '_', 'I', '3', '2', 0,
  /* 1036 */ 'M', 'U', 'L', '_', 'I', '3', '2', 0,
  /* 1044 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'X', 'C', 'E', 'P', 'T', 'I', 'O', 'N', '_', 'I', '3', '2', 0,
  /* 1066 */ 'D', 'R', 'O', 'P', '_', 'I', '3', '2', 0,
  /* 1075 */ 'E', 'Q', '_', 'I', '3', '2', 0,
  /* 1082 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0,
  /* 1105 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0,
  /* 1127 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0,
  /* 1146 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'O', 'R', '_', 'I', '3', '2', 0,
  /* 1168 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'O', 'R', '_', 'I', '3', '2', 0,
  /* 1189 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'O', 'R', '_', 'I', '3', '2', 0,
  /* 1207 */ 'R', 'O', 'T', 'R', '_', 'I', '3', '2', 0,
  /* 1216 */ 'L', 'O', 'A', 'D', '1', '6', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1229 */ 'I', '3', '2', '_', 'E', 'X', 'T', 'E', 'N', 'D', '1', '6', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1248 */ 'L', 'O', 'A', 'D', '8', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1260 */ 'I', '3', '2', '_', 'E', 'X', 'T', 'E', 'N', 'D', '8', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1278 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1295 */ 'G', 'E', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1304 */ 'L', 'E', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1313 */ 'R', 'E', 'M', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1323 */ 'S', 'H', 'R', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1333 */ 'G', 'T', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1342 */ 'L', 'T', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1351 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1369 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1387 */ 'D', 'I', 'V', '_', 'S', '_', 'I', '3', '2', 0,
  /* 1397 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '3', '2', 0,
  /* 1408 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '3', '2', 0,
  /* 1423 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '3', '2', 0,
  /* 1437 */ 'F', '3', '2', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'I', '3', '2', 0,
  /* 1457 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '3', '2', 0,
  /* 1472 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '3', '2', 0,
  /* 1486 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'W', 'A', 'I', 'T', '_', 'I', '3', '2', 0,
  /* 1502 */ 'P', 'O', 'P', 'C', 'N', 'T', '_', 'I', '3', '2', 0,
  /* 1513 */ 'C', 'O', 'N', 'S', 'T', '_', 'I', '3', '2', 0,
  /* 1523 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '1', '6', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1543 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '8', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1562 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1579 */ 'G', 'E', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1588 */ 'L', 'E', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1597 */ 'R', 'E', 'M', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1607 */ 'S', 'H', 'R', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1617 */ 'G', 'T', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1626 */ 'L', 'T', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1635 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1653 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1671 */ 'D', 'I', 'V', '_', 'U', '_', 'I', '3', '2', 0,
  /* 1681 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'G', 'R', 'O', 'W', '_', 'I', '3', '2', 0,
  /* 1697 */ 'C', 'O', 'P', 'Y', '_', 'I', '3', '2', 0,
  /* 1706 */ 'C', 'L', 'Z', '_', 'I', '3', '2', 0,
  /* 1714 */ 'E', 'Q', 'Z', '_', 'I', '3', '2', 0,
  /* 1722 */ 'C', 'T', 'Z', '_', 'I', '3', '2', 0,
  /* 1730 */ 'f', 'p', '_', 't', 'o', '_', 's', 'i', 'n', 't', '_', 'v', '4', 'i', '3', '2', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1753 */ 'f', 'p', '_', 't', 'o', '_', 'u', 'i', 'n', 't', '_', 'v', '4', 'i', '3', '2', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1776 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1793 */ 'Q', 'F', 'M', 'A', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1804 */ 'S', 'U', 'B', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1814 */ 'A', 'D', 'D', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1824 */ 'G', 'E', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1833 */ 'L', 'E', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1842 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1861 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1880 */ 'N', 'E', 'G', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1890 */ 'C', 'A', 'L', 'L', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1901 */ 'M', 'U', 'L', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1911 */ 'M', 'I', 'N', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1921 */ 'E', 'Q', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1930 */ 'A', 'B', 'S', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1940 */ 'Q', 'F', 'M', 'S', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1951 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1963 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 1979 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2000 */ 'G', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2009 */ 'L', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2018 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2033 */ 'S', 'Q', 'R', 'T', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2044 */ 'D', 'I', 'V', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2054 */ 'M', 'A', 'X', '_', 'v', '4', 'f', '3', '2', 0,
  /* 2064 */ 'C', 'A', 'L', 'L', '_', 'f', '3', '2', 0,
  /* 2073 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'f', '3', '2', 0,
  /* 2092 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'f', '3', '2', 0,
  /* 2105 */ 's', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '4', 'f', '3', '2', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2128 */ 'u', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '4', 'f', '3', '2', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2151 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2168 */ 'S', 'U', 'B', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2178 */ 'A', 'D', 'D', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2188 */ 'A', 'N', 'D', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2198 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2217 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2236 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2250 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2264 */ 'N', 'E', 'G', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2274 */ 'S', 'H', 'L', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2284 */ 'C', 'A', 'L', 'L', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2295 */ 'M', 'U', 'L', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2305 */ 'E', 'Q', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2314 */ 'X', 'O', 'R', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2324 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2344 */ 'G', 'E', '_', 'S', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2355 */ 'L', 'E', '_', 'S', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2366 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2378 */ 'G', 'T', '_', 'S', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2389 */ 'L', 'T', '_', 'S', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2400 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2412 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2428 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2449 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2464 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2477 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2497 */ 'G', 'E', '_', 'U', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2508 */ 'L', 'E', '_', 'U', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2519 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2531 */ 'G', 'T', '_', 'U', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2542 */ 'L', 'T', '_', 'U', '_', 'v', '4', 'i', '3', '2', 0,
  /* 2553 */ 'C', 'A', 'L', 'L', '_', 'i', '3', '2', 0,
  /* 2562 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'i', '3', '2', 0,
  /* 2581 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'i', '3', '2', 0,
  /* 2594 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
  /* 2602 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
  /* 2610 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '6', '4', 'x', '2', 0,
  /* 2627 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '6', '4', 0,
  /* 2646 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '6', '4', 0,
  /* 2665 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '6', '4', 0,
  /* 2684 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '6', '4', 0,
  /* 2703 */ 'S', 'U', 'B', '_', 'F', '6', '4', 0,
  /* 2711 */ 'T', 'R', 'U', 'N', 'C', '_', 'F', '6', '4', 0,
  /* 2721 */ 'L', 'O', 'A', 'D', '_', 'F', '6', '4', 0,
  /* 2730 */ 'A', 'D', 'D', '_', 'F', '6', '4', 0,
  /* 2738 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'F', '6', '4', 0,
  /* 2752 */ 'G', 'E', '_', 'F', '6', '4', 0,
  /* 2759 */ 'L', 'E', '_', 'F', '6', '4', 0,
  /* 2766 */ 'N', 'E', '_', 'F', '6', '4', 0,
  /* 2773 */ 'S', 'T', 'O', 'R', 'E', '_', 'F', '6', '4', 0,
  /* 2783 */ 'F', '3', '2', '_', 'D', 'E', 'M', 'O', 'T', 'E', '_', 'F', '6', '4', 0,
  /* 2798 */ 'N', 'E', 'G', '_', 'F', '6', '4', 0,
  /* 2806 */ 'C', 'E', 'I', 'L', '_', 'F', '6', '4', 0,
  /* 2815 */ 'M', 'U', 'L', '_', 'F', '6', '4', 0,
  /* 2823 */ 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', '_', 'F', '6', '4', 0,
  /* 2836 */ 'M', 'I', 'N', '_', 'F', '6', '4', 0,
  /* 2844 */ 'D', 'R', 'O', 'P', '_', 'F', '6', '4', 0,
  /* 2853 */ 'E', 'Q', '_', 'F', '6', '4', 0,
  /* 2860 */ 'F', 'L', 'O', 'O', 'R', '_', 'F', '6', '4', 0,
  /* 2870 */ 'A', 'B', 'S', '_', 'F', '6', '4', 0,
  /* 2878 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '6', '4', 0,
  /* 2894 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '6', '4', 0,
  /* 2910 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '6', '4', 0,
  /* 2930 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '6', '4', 0,
  /* 2950 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '6', '4', 0,
  /* 2970 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '6', '4', 0,
  /* 2990 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '6', '4', 0,
  /* 3001 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '6', '4', 0,
  /* 3016 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '6', '4', 0,
  /* 3030 */ 'I', '6', '4', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'F', '6', '4', 0,
  /* 3050 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '6', '4', 0,
  /* 3065 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '6', '4', 0,
  /* 3079 */ 'G', 'T', '_', 'F', '6', '4', 0,
  /* 3086 */ 'L', 'T', '_', 'F', '6', '4', 0,
  /* 3093 */ 'S', 'Q', 'R', 'T', '_', 'F', '6', '4', 0,
  /* 3102 */ 'N', 'E', 'A', 'R', 'E', 'S', 'T', '_', 'F', '6', '4', 0,
  /* 3114 */ 'C', 'O', 'N', 'S', 'T', '_', 'F', '6', '4', 0,
  /* 3124 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '6', '4', 0,
  /* 3140 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '6', '4', 0,
  /* 3156 */ 'D', 'I', 'V', '_', 'F', '6', '4', 0,
  /* 3164 */ 'M', 'A', 'X', '_', 'F', '6', '4', 0,
  /* 3172 */ 'C', 'O', 'P', 'Y', '_', 'F', '6', '4', 0,
  /* 3181 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '3', '2', '_', 'I', '6', '4', 0,
  /* 3200 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '1', '6', '_', 'I', '6', '4', 0,
  /* 3219 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '8', '_', 'I', '6', '4', 0,
  /* 3237 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
  /* 3260 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
  /* 3283 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
  /* 3305 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
  /* 3324 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'I', '6', '4', 0,
  /* 3340 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
  /* 3363 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
  /* 3386 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
  /* 3408 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
  /* 3427 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
  /* 3450 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
  /* 3473 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
  /* 3495 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
  /* 3514 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'I', '6', '4', 0,
  /* 3528 */ 'B', 'R', '_', 'T', 'A', 'B', 'L', 'E', '_', 'I', '6', '4', 0,
  /* 3541 */ 'N', 'E', '_', 'I', '6', '4', 0,
  /* 3548 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '_', 'I', '6', '4', 0,
  /* 3565 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3592 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3619 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3645 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3668 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3692 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3716 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3739 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', 0,
  /* 3759 */ 'S', 'H', 'L', '_', 'I', '6', '4', 0,
  /* 3767 */ 'R', 'O', 'T', 'L', '_', 'I', '6', '4', 0,
  /* 3776 */ 'M', 'U', 'L', '_', 'I', '6', '4', 0,
  /* 3784 */ 'I', '3', '2', '_', 'W', 'R', 'A', 'P', '_', 'I', '6', '4', 0,
  /* 3797 */ 'D', 'R', 'O', 'P', '_', 'I', '6', '4', 0,
  /* 3806 */ 'E', 'Q', '_', 'I', '6', '4', 0,
  /* 3813 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3836 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3859 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3881 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3900 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3922 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3944 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3965 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'O', 'R', '_', 'I', '6', '4', 0,
  /* 3983 */ 'R', 'O', 'T', 'R', '_', 'I', '6', '4', 0,
  /* 3992 */ 'L', 'O', 'A', 'D', '3', '2', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4005 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '3', '2', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4024 */ 'L', 'O', 'A', 'D', '1', '6', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4037 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '1', '6', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4056 */ 'L', 'O', 'A', 'D', '8', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4068 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '8', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4086 */ 'G', 'E', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4095 */ 'L', 'E', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4104 */ 'R', 'E', 'M', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4114 */ 'S', 'H', 'R', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4124 */ 'G', 'T', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4133 */ 'L', 'T', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4142 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4160 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4178 */ 'D', 'I', 'V', '_', 'S', '_', 'I', '6', '4', 0,
  /* 4188 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0,
  /* 4199 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '6', '4', 0,
  /* 4214 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '6', '4', 0,
  /* 4228 */ 'F', '6', '4', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'I', '6', '4', 0,
  /* 4248 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '6', '4', 0,
  /* 4263 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '6', '4', 0,
  /* 4277 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'W', 'A', 'I', 'T', '_', 'I', '6', '4', 0,
  /* 4293 */ 'P', 'O', 'P', 'C', 'N', 'T', '_', 'I', '6', '4', 0,
  /* 4304 */ 'C', 'O', 'N', 'S', 'T', '_', 'I', '6', '4', 0,
  /* 4314 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '3', '2', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4334 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '1', '6', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4354 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '8', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4373 */ 'G', 'E', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4382 */ 'L', 'E', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4391 */ 'R', 'E', 'M', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4401 */ 'S', 'H', 'R', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4411 */ 'G', 'T', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4420 */ 'L', 'T', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4429 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4447 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4465 */ 'D', 'I', 'V', '_', 'U', '_', 'I', '6', '4', 0,
  /* 4475 */ 'C', 'O', 'P', 'Y', '_', 'I', '6', '4', 0,
  /* 4484 */ 'C', 'L', 'Z', '_', 'I', '6', '4', 0,
  /* 4492 */ 'E', 'Q', 'Z', '_', 'I', '6', '4', 0,
  /* 4500 */ 'C', 'T', 'Z', '_', 'I', '6', '4', 0,
  /* 4508 */ 'f', 'p', '_', 't', 'o', '_', 's', 'i', 'n', 't', '_', 'v', '2', 'i', '6', '4', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4531 */ 'f', 'p', '_', 't', 'o', '_', 'u', 'i', 'n', 't', '_', 'v', '2', 'i', '6', '4', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4554 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4571 */ 'Q', 'F', 'M', 'A', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4582 */ 'S', 'U', 'B', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4592 */ 'A', 'D', 'D', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4602 */ 'G', 'E', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4611 */ 'L', 'E', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4620 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4639 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4658 */ 'N', 'E', 'G', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4668 */ 'C', 'A', 'L', 'L', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4679 */ 'M', 'U', 'L', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4689 */ 'M', 'I', 'N', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4699 */ 'E', 'Q', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4708 */ 'A', 'B', 'S', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4718 */ 'Q', 'F', 'M', 'S', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4729 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4741 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4757 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4778 */ 'G', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4787 */ 'L', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4796 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4811 */ 'S', 'Q', 'R', 'T', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4822 */ 'D', 'I', 'V', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4832 */ 'M', 'A', 'X', '_', 'v', '2', 'f', '6', '4', 0,
  /* 4842 */ 'C', 'A', 'L', 'L', '_', 'f', '6', '4', 0,
  /* 4851 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'f', '6', '4', 0,
  /* 4870 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'f', '6', '4', 0,
  /* 4883 */ 's', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '2', 'f', '6', '4', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4906 */ 'u', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '2', 'f', '6', '4', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4929 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4946 */ 'S', 'U', 'B', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4956 */ 'A', 'D', 'D', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4966 */ 'A', 'N', 'D', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4976 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'i', '6', '4', 0,
  /* 4995 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5014 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5028 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5042 */ 'N', 'E', 'G', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5052 */ 'S', 'H', 'L', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5062 */ 'C', 'A', 'L', 'L', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5073 */ 'X', 'O', 'R', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5083 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5103 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5115 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5127 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5143 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5164 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5179 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5192 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5212 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '2', 'i', '6', '4', 0,
  /* 5224 */ 'C', 'A', 'L', 'L', '_', 'i', '6', '4', 0,
  /* 5233 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'i', '6', '4', 0,
  /* 5252 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'i', '6', '4', 0,
  /* 5265 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '3', '2', 'x', '4', 0,
  /* 5282 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5321 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5359 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5400 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5440 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5457 */ 'S', 'U', 'B', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5467 */ 'A', 'D', 'D', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5477 */ 'A', 'N', 'D', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5487 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5506 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5520 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5534 */ 'N', 'E', 'G', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5544 */ 'S', 'H', 'L', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5554 */ 'C', 'A', 'L', 'L', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5565 */ 'M', 'U', 'L', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5575 */ 'E', 'Q', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5584 */ 'X', 'O', 'R', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5594 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5614 */ 'G', 'E', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5625 */ 'L', 'E', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5636 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5648 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5664 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5680 */ 'G', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5691 */ 'L', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5702 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'S', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5717 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5729 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5745 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5766 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5781 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5794 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5814 */ 'G', 'E', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5825 */ 'L', 'E', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5836 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5848 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5864 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5880 */ 'G', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5891 */ 'L', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5902 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'U', '_', 'v', '8', 'i', '1', '6', 0,
  /* 5917 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '8', 'x', '1', '6', 0,
  /* 5934 */ 'L', 'O', 'A', 'D', '_', 'V', '1', '2', '8', 0,
  /* 5944 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'V', '1', '2', '8', 0,
  /* 5959 */ 'S', 'T', 'O', 'R', 'E', '_', 'V', '1', '2', '8', 0,
  /* 5970 */ 'D', 'R', 'O', 'P', '_', 'V', '1', '2', '8', 0,
  /* 5980 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'V', '1', '2', '8', 0,
  /* 5996 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'V', '1', '2', '8', 0,
  /* 6011 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'V', '1', '2', '8', 0,
  /* 6027 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'V', '1', '2', '8', 0,
  /* 6042 */ 'C', 'O', 'P', 'Y', '_', 'V', '1', '2', '8', 0,
  /* 6052 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6091 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6129 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6170 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6210 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6227 */ 'S', 'U', 'B', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6237 */ 'A', 'D', 'D', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6247 */ 'A', 'N', 'D', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6257 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6276 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6290 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6304 */ 'N', 'E', 'G', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6314 */ 'S', 'H', 'L', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6324 */ 'C', 'A', 'L', 'L', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6335 */ 'M', 'U', 'L', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6345 */ 'E', 'Q', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6354 */ 'X', 'O', 'R', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6364 */ 'G', 'E', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6375 */ 'L', 'E', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6386 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6398 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6414 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6430 */ 'G', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6441 */ 'L', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6452 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'S', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6467 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6479 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6495 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6516 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6531 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6544 */ 'G', 'E', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6555 */ 'L', 'E', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6566 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6578 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6594 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6610 */ 'G', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6621 */ 'L', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6632 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'U', '_', 'v', '1', '6', 'i', '8', 0,
  /* 6647 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '1', '6', 'x', '8', 0,
  /* 6664 */ 'G', '_', 'F', 'M', 'A', 0,
  /* 6670 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
  /* 6677 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'S', 'U', 'B', 0,
  /* 6694 */ 'G', '_', 'S', 'U', 'B', 0,
  /* 6700 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
  /* 6716 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
  /* 6728 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
  /* 6738 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 6756 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 6764 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
  /* 6785 */ 'G', '_', 'D', 'Y', 'N', '_', 'S', 'T', 'A', 'C', 'K', 'A', 'L', 'L', 'O', 'C', 0,
  /* 6802 */ 'G', '_', 'F', 'M', 'A', 'D', 0,
  /* 6809 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 6828 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 6839 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 6858 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
  /* 6869 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'L', 'O', 'A', 'D', 0,
  /* 6884 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
  /* 6891 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
  /* 6898 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'A', 'D', 'D', 0,
  /* 6915 */ 'G', '_', 'A', 'D', 'D', 0,
  /* 6921 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
  /* 6937 */ 'C', 'A', 'L', 'L', '_', 'V', 'O', 'I', 'D', 0,
  /* 6947 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'V', 'O', 'I', 'D', 0,
  /* 6967 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
  /* 6984 */ 'G', '_', 'A', 'N', 'D', 0,
  /* 6990 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
  /* 7006 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
  /* 7019 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
  /* 7028 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
  /* 7046 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
  /* 7063 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
  /* 7071 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
  /* 7079 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'F', 'E', 'N', 'C', 'E', 0,
  /* 7092 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0,
  /* 7100 */ 'C', 'O', 'M', 'P', 'I', 'L', 'E', 'R', '_', 'F', 'E', 'N', 'C', 'E', 0,
  /* 7115 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
  /* 7128 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
  /* 7136 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
  /* 7144 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
  /* 7159 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
  /* 7174 */ 'U', 'N', 'R', 'E', 'A', 'C', 'H', 'A', 'B', 'L', 'E', 0,
  /* 7186 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0,
  /* 7199 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
  /* 7206 */ 'S', 'H', 'U', 'F', 'F', 'L', 'E', 0,
  /* 7214 */ 'S', 'W', 'I', 'Z', 'Z', 'L', 'E', 0,
  /* 7222 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
  /* 7235 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'T', 'O', 'R', 'E', 0,
  /* 7251 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
  /* 7259 */ 'E', 'L', 'S', 'E', 0,
  /* 7264 */ 'G', '_', 'B', 'I', 'T', 'R', 'E', 'V', 'E', 'R', 'S', 'E', 0,
  /* 7277 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
  /* 7287 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
  /* 7302 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
  /* 7318 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
  /* 7336 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
  /* 7354 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
  /* 7369 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7386 */ 'D', 'R', 'O', 'P', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7398 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7412 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7430 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7447 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7465 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7482 */ 'C', 'O', 'P', 'Y', '_', 'E', 'X', 'N', 'R', 'E', 'F', 0,
  /* 7494 */ 'E', 'N', 'D', '_', 'I', 'F', 0,
  /* 7501 */ 'B', 'R', '_', 'I', 'F', 0,
  /* 7507 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
  /* 7514 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
  /* 7529 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
  /* 7543 */ 'G', '_', 'S', 'E', 'X', 'T', '_', 'I', 'N', 'R', 'E', 'G', 0,
  /* 7556 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
  /* 7570 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
  /* 7587 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
  /* 7604 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
  /* 7611 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
  /* 7619 */ 'R', 'E', 'T', 'H', 'R', 'O', 'W', '_', 'I', 'N', '_', 'C', 'A', 'T', 'C', 'H', 0,
  /* 7636 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
  /* 7644 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
  /* 7652 */ 'G', '_', 'P', 'H', 'I', 0,
  /* 7658 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
  /* 7667 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
  /* 7676 */ 'E', 'N', 'D', '_', 'B', 'L', 'O', 'C', 'K', 0,
  /* 7686 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
  /* 7697 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 7706 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 7716 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 7725 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
  /* 7742 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
  /* 7762 */ 'G', '_', 'S', 'H', 'L', 0,
  /* 7768 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
  /* 7776 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
  /* 7796 */ 'R', 'E', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 7805 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 7832 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
  /* 7853 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
  /* 7865 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'F', 'I', 'L', 'L', 0,
  /* 7877 */ 'K', 'I', 'L', 'L', 0,
  /* 7882 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
  /* 7889 */ 'G', '_', 'M', 'U', 'L', 0,
  /* 7895 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
  /* 7902 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
  /* 7909 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
  /* 7916 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
  /* 7926 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0,
  /* 7937 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0,
  /* 7948 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0,
  /* 7958 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0,
  /* 7968 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0,
  /* 7980 */ 'G', '_', 'S', 'M', 'I', 'N', 0,
  /* 7987 */ 'G', '_', 'U', 'M', 'I', 'N', 0,
  /* 7994 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
  /* 8011 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
  /* 8027 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
  /* 8034 */ 'E', 'N', 'D', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', 0,
  /* 8047 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
  /* 8063 */ 'F', 'A', 'L', 'L', 'T', 'H', 'R', 'O', 'U', 'G', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', 0,
  /* 8082 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
  /* 8099 */ 'B', 'R', '_', 'O', 'N', '_', 'E', 'X', 'N', 0,
  /* 8109 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
  /* 8117 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
  /* 8125 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
  /* 8133 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
  /* 8141 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
  /* 8149 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
  /* 8157 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
  /* 8166 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
  /* 8174 */ 'G', '_', 'G', 'E', 'P', 0,
  /* 8180 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
  /* 8189 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
  /* 8198 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
  /* 8205 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
  /* 8212 */ 'N', 'O', 'P', 0,
  /* 8216 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', 0,
  /* 8225 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
  /* 8233 */ 'D', 'A', 'T', 'A', '_', 'D', 'R', 'O', 'P', 0,
  /* 8243 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
  /* 8256 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
  /* 8268 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
  /* 8283 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
  /* 8290 */ 'G', '_', 'B', 'R', 0,
  /* 8295 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
  /* 8308 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
  /* 8321 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
  /* 8346 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
  /* 8353 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
  /* 8360 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
  /* 8369 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
  /* 8384 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
  /* 8401 */ 'G', '_', 'X', 'O', 'R', 0,
  /* 8407 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
  /* 8423 */ 'G', '_', 'O', 'R', 0,
  /* 8428 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
  /* 8443 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
  /* 8454 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
  /* 8461 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
  /* 8478 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
  /* 8493 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
  /* 8500 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
  /* 8517 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
  /* 8534 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
  /* 8564 */ 'B', 'R', '_', 'U', 'N', 'L', 'E', 'S', 'S', 0,
  /* 8574 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
  /* 8601 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8622 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8643 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8664 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8685 */ 'S', 'U', 'B', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8695 */ 'T', 'R', 'U', 'N', 'C', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8707 */ 'L', 'O', 'A', 'D', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8718 */ 'A', 'D', 'D', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8728 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8744 */ 'G', 'E', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8753 */ 'L', 'E', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8762 */ 'N', 'E', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8771 */ 'S', 'T', 'O', 'R', 'E', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8783 */ 'F', '6', '4', '_', 'P', 'R', 'O', 'M', 'O', 'T', 'E', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8801 */ 'N', 'E', 'G', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8811 */ 'C', 'E', 'I', 'L', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8822 */ 'M', 'U', 'L', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8832 */ 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8847 */ 'M', 'I', 'N', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8857 */ 'D', 'R', 'O', 'P', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8868 */ 'E', 'Q', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8877 */ 'F', 'L', 'O', 'O', 'R', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8889 */ 'A', 'B', 'S', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8899 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8917 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8935 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8957 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 8979 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9001 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9023 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9036 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9053 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9069 */ 'I', '3', '2', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9091 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9108 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9124 */ 'G', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9133 */ 'L', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9142 */ 'S', 'Q', 'R', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9153 */ 'N', 'E', 'A', 'R', 'E', 'S', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9167 */ 'C', 'O', 'N', 'S', 'T', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9179 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9197 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9215 */ 'D', 'I', 'V', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9225 */ 'M', 'A', 'X', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9235 */ 'C', 'O', 'P', 'Y', '_', 'F', '3', '2', '_', 'S', 0,
  /* 9246 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '1', '6', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9267 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '8', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9287 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9312 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9336 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'S', 'U', 'B', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9357 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9375 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9400 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9424 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'D', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9445 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9470 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9494 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9515 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9531 */ 'B', 'R', '_', 'T', 'A', 'B', 'L', 'E', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9546 */ 'N', 'E', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9555 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9574 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'S', 'I', 'Z', 'E', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9592 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9621 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9649 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9674 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9700 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9725 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9747 */ 'S', 'H', 'L', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9757 */ 'R', 'O', 'T', 'L', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9768 */ 'M', 'U', 'L', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9778 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'E', 'X', 'C', 'E', 'P', 'T', 'I', 'O', 'N', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9802 */ 'D', 'R', 'O', 'P', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9813 */ 'E', 'Q', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9822 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9847 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9871 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'O', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9892 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'O', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9916 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'O', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9939 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'O', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9959 */ 'R', 'O', 'T', 'R', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9970 */ 'L', 'O', 'A', 'D', '1', '6', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 9985 */ 'I', '3', '2', '_', 'E', 'X', 'T', 'E', 'N', 'D', '1', '6', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10006 */ 'L', 'O', 'A', 'D', '8', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10020 */ 'I', '3', '2', '_', 'E', 'X', 'T', 'E', 'N', 'D', '8', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10040 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10059 */ 'G', 'E', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10070 */ 'L', 'E', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10081 */ 'R', 'E', 'M', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10093 */ 'S', 'H', 'R', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10105 */ 'G', 'T', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10116 */ 'L', 'T', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10127 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10147 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10167 */ 'D', 'I', 'V', '_', 'S', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10179 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10192 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10209 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10225 */ 'F', '3', '2', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10247 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10264 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10280 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'W', 'A', 'I', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10298 */ 'P', 'O', 'P', 'C', 'N', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10311 */ 'C', 'O', 'N', 'S', 'T', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10323 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '1', '6', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10345 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '8', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10366 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10385 */ 'G', 'E', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10396 */ 'L', 'E', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10407 */ 'R', 'E', 'M', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10419 */ 'S', 'H', 'R', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10431 */ 'G', 'T', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10442 */ 'L', 'T', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10453 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10473 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10493 */ 'D', 'I', 'V', '_', 'U', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10505 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'G', 'R', 'O', 'W', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10523 */ 'C', 'O', 'P', 'Y', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10534 */ 'C', 'L', 'Z', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10544 */ 'E', 'Q', 'Z', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10554 */ 'C', 'T', 'Z', '_', 'I', '3', '2', '_', 'S', 0,
  /* 10564 */ 'f', 'p', '_', 't', 'o', '_', 's', 'i', 'n', 't', '_', 'v', '4', 'i', '3', '2', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10589 */ 'f', 'p', '_', 't', 'o', '_', 'u', 'i', 'n', 't', '_', 'v', '4', 'i', '3', '2', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10614 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10633 */ 'Q', 'F', 'M', 'A', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10646 */ 'S', 'U', 'B', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10658 */ 'A', 'D', 'D', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10670 */ 'G', 'E', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10681 */ 'L', 'E', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10692 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10713 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10734 */ 'N', 'E', 'G', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10746 */ 'C', 'A', 'L', 'L', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10759 */ 'M', 'U', 'L', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10771 */ 'M', 'I', 'N', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10783 */ 'E', 'Q', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10794 */ 'A', 'B', 'S', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10806 */ 'Q', 'F', 'M', 'S', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10819 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10833 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10851 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10874 */ 'G', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10885 */ 'L', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10896 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10913 */ 'S', 'Q', 'R', 'T', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10926 */ 'D', 'I', 'V', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10938 */ 'M', 'A', 'X', '_', 'v', '4', 'f', '3', '2', '_', 'S', 0,
  /* 10950 */ 'C', 'A', 'L', 'L', '_', 'f', '3', '2', '_', 'S', 0,
  /* 10961 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'f', '3', '2', '_', 'S', 0,
  /* 10982 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'f', '3', '2', '_', 'S', 0,
  /* 10997 */ 's', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '4', 'f', '3', '2', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11022 */ 'u', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '4', 'f', '3', '2', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11047 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11066 */ 'S', 'U', 'B', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11078 */ 'A', 'D', 'D', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11090 */ 'A', 'N', 'D', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11102 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11123 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11144 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11160 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11176 */ 'N', 'E', 'G', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11188 */ 'S', 'H', 'L', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11200 */ 'C', 'A', 'L', 'L', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11213 */ 'M', 'U', 'L', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11225 */ 'E', 'Q', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11236 */ 'X', 'O', 'R', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11248 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11270 */ 'G', 'E', '_', 'S', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11283 */ 'L', 'E', '_', 'S', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11296 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11310 */ 'G', 'T', '_', 'S', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11323 */ 'L', 'T', '_', 'S', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11336 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11350 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11368 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11391 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11408 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11423 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11445 */ 'G', 'E', '_', 'U', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11458 */ 'L', 'E', '_', 'U', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11471 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11485 */ 'G', 'T', '_', 'U', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11498 */ 'L', 'T', '_', 'U', '_', 'v', '4', 'i', '3', '2', '_', 'S', 0,
  /* 11511 */ 'C', 'A', 'L', 'L', '_', 'i', '3', '2', '_', 'S', 0,
  /* 11522 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'i', '3', '2', '_', 'S', 0,
  /* 11543 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'i', '3', '2', '_', 'S', 0,
  /* 11558 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '6', '4', 'x', '2', '_', 'S', 0,
  /* 11577 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11598 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '3', '2', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11619 */ 'F', 'P', '_', 'T', 'O', '_', 'S', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11640 */ 'F', 'P', '_', 'T', 'O', '_', 'U', 'I', 'N', 'T', '_', 'I', '6', '4', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11661 */ 'S', 'U', 'B', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11671 */ 'T', 'R', 'U', 'N', 'C', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11683 */ 'L', 'O', 'A', 'D', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11694 */ 'A', 'D', 'D', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11704 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11720 */ 'G', 'E', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11729 */ 'L', 'E', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11738 */ 'N', 'E', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11747 */ 'S', 'T', 'O', 'R', 'E', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11759 */ 'F', '3', '2', '_', 'D', 'E', 'M', 'O', 'T', 'E', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11776 */ 'N', 'E', 'G', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11786 */ 'C', 'E', 'I', 'L', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11797 */ 'M', 'U', 'L', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11807 */ 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11822 */ 'M', 'I', 'N', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11832 */ 'D', 'R', 'O', 'P', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11843 */ 'E', 'Q', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11852 */ 'F', 'L', 'O', 'O', 'R', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11864 */ 'A', 'B', 'S', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11874 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11892 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11910 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11932 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'S', 'A', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11954 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11976 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'S', 'A', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 11998 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12011 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12028 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12044 */ 'I', '6', '4', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12066 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12083 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12099 */ 'G', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12108 */ 'L', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12117 */ 'S', 'Q', 'R', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12128 */ 'N', 'E', 'A', 'R', 'E', 'S', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12142 */ 'C', 'O', 'N', 'S', 'T', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12154 */ 'I', '3', '2', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12172 */ 'I', '6', '4', '_', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12190 */ 'D', 'I', 'V', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12200 */ 'M', 'A', 'X', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12210 */ 'C', 'O', 'P', 'Y', '_', 'F', '6', '4', '_', 'S', 0,
  /* 12221 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '3', '2', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12242 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '1', '6', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12263 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '8', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12283 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12308 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12333 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12357 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12378 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12396 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12421 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12446 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12470 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12491 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12516 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12541 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12565 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12586 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12602 */ 'B', 'R', '_', 'T', 'A', 'B', 'L', 'E', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12617 */ 'N', 'E', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12626 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'T', 'O', 'R', 'E', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12645 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12674 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12703 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12731 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12756 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12782 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12808 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12833 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12855 */ 'S', 'H', 'L', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12865 */ 'R', 'O', 'T', 'L', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12876 */ 'M', 'U', 'L', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12886 */ 'I', '3', '2', '_', 'W', 'R', 'A', 'P', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12901 */ 'D', 'R', 'O', 'P', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12912 */ 'E', 'Q', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12921 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12946 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12971 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 12995 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13016 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '3', '2', '_', 'U', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13040 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '1', '6', '_', 'U', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13064 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '8', '_', 'U', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13087 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'R', 'M', 'W', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13107 */ 'R', 'O', 'T', 'R', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13118 */ 'L', 'O', 'A', 'D', '3', '2', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13133 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '3', '2', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13154 */ 'L', 'O', 'A', 'D', '1', '6', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13169 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '1', '6', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13190 */ 'L', 'O', 'A', 'D', '8', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13204 */ 'I', '6', '4', '_', 'E', 'X', 'T', 'E', 'N', 'D', '8', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13224 */ 'G', 'E', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13235 */ 'L', 'E', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13246 */ 'R', 'E', 'M', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13258 */ 'S', 'H', 'R', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13270 */ 'G', 'T', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13281 */ 'L', 'T', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13292 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13312 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13332 */ 'D', 'I', 'V', '_', 'S', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13344 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13357 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13374 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13390 */ 'F', '6', '4', '_', 'R', 'E', 'I', 'N', 'T', 'E', 'R', 'P', 'R', 'E', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13412 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13429 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13445 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'W', 'A', 'I', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13463 */ 'P', 'O', 'P', 'C', 'N', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13476 */ 'C', 'O', 'N', 'S', 'T', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13488 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '3', '2', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13510 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '1', '6', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13532 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '8', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13553 */ 'G', 'E', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13564 */ 'L', 'E', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13575 */ 'R', 'E', 'M', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13587 */ 'S', 'H', 'R', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13599 */ 'G', 'T', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13610 */ 'L', 'T', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13621 */ 'F', '3', '2', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13641 */ 'F', '6', '4', '_', 'C', 'O', 'N', 'V', 'E', 'R', 'T', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13661 */ 'D', 'I', 'V', '_', 'U', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13673 */ 'C', 'O', 'P', 'Y', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13684 */ 'C', 'L', 'Z', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13694 */ 'E', 'Q', 'Z', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13704 */ 'C', 'T', 'Z', '_', 'I', '6', '4', '_', 'S', 0,
  /* 13714 */ 'f', 'p', '_', 't', 'o', '_', 's', 'i', 'n', 't', '_', 'v', '2', 'i', '6', '4', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13739 */ 'f', 'p', '_', 't', 'o', '_', 'u', 'i', 'n', 't', '_', 'v', '2', 'i', '6', '4', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13764 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13783 */ 'Q', 'F', 'M', 'A', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13796 */ 'S', 'U', 'B', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13808 */ 'A', 'D', 'D', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13820 */ 'G', 'E', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13831 */ 'L', 'E', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13842 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13863 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13884 */ 'N', 'E', 'G', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13896 */ 'C', 'A', 'L', 'L', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13909 */ 'M', 'U', 'L', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13921 */ 'M', 'I', 'N', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13933 */ 'E', 'Q', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13944 */ 'A', 'B', 'S', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13956 */ 'Q', 'F', 'M', 'S', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13969 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 13983 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14001 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14024 */ 'G', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14035 */ 'L', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14046 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14063 */ 'S', 'Q', 'R', 'T', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14076 */ 'D', 'I', 'V', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14088 */ 'M', 'A', 'X', '_', 'v', '2', 'f', '6', '4', '_', 'S', 0,
  /* 14100 */ 'C', 'A', 'L', 'L', '_', 'f', '6', '4', '_', 'S', 0,
  /* 14111 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'f', '6', '4', '_', 'S', 0,
  /* 14132 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'f', '6', '4', '_', 'S', 0,
  /* 14147 */ 's', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '2', 'f', '6', '4', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14172 */ 'u', 'i', 'n', 't', '_', 't', 'o', '_', 'f', 'p', '_', 'v', '2', 'f', '6', '4', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14197 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14216 */ 'S', 'U', 'B', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14228 */ 'A', 'D', 'D', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14240 */ 'A', 'N', 'D', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14252 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14273 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14294 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14310 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14326 */ 'N', 'E', 'G', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14338 */ 'S', 'H', 'L', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14350 */ 'C', 'A', 'L', 'L', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14363 */ 'X', 'O', 'R', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14375 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14397 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14411 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14425 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14443 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14466 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14483 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14498 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14520 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '2', 'i', '6', '4', '_', 'S', 0,
  /* 14534 */ 'C', 'A', 'L', 'L', '_', 'i', '6', '4', '_', 'S', 0,
  /* 14545 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'i', '6', '4', '_', 'S', 0,
  /* 14566 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'i', '6', '4', '_', 'S', 0,
  /* 14581 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '3', '2', 'x', '4', '_', 'S', 0,
  /* 14600 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14641 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14681 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14724 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '4', 'i', '3', '2', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14766 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14785 */ 'S', 'U', 'B', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14797 */ 'A', 'D', 'D', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14809 */ 'A', 'N', 'D', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14821 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14842 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14858 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14874 */ 'N', 'E', 'G', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14886 */ 'S', 'H', 'L', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14898 */ 'C', 'A', 'L', 'L', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14911 */ 'M', 'U', 'L', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14923 */ 'E', 'Q', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14934 */ 'X', 'O', 'R', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14946 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14968 */ 'G', 'E', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14981 */ 'L', 'E', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 14994 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15008 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15026 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15044 */ 'G', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15057 */ 'L', 'T', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15070 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'S', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15087 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15101 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15119 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15142 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15159 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15174 */ 'L', 'O', 'A', 'D', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15196 */ 'G', 'E', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15209 */ 'L', 'E', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15222 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15236 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15254 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15272 */ 'G', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15285 */ 'L', 'T', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15298 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'U', '_', 'v', '8', 'i', '1', '6', '_', 'S', 0,
  /* 15315 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '8', 'x', '1', '6', '_', 'S', 0,
  /* 15334 */ 'L', 'O', 'A', 'D', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15346 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15363 */ 'S', 'T', 'O', 'R', 'E', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15376 */ 'D', 'R', 'O', 'P', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15388 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15406 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15423 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15441 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15458 */ 'C', 'O', 'P', 'Y', '_', 'V', '1', '2', '8', '_', 'S', 0,
  /* 15470 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15511 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15551 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'h', 'i', 'g', 'h', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15594 */ 'i', 'n', 't', '_', 'w', 'a', 's', 'm', '_', 'w', 'i', 'd', 'e', 'n', '_', 'l', 'o', 'w', '_', 'u', 'n', 's', 'i', 'g', 'n', 'e', 'd', '_', 'v', '8', 'i', '1', '6', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15636 */ 'C', 'O', 'N', 'S', 'T', '_', 'V', '1', '2', '8', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15655 */ 'S', 'U', 'B', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15667 */ 'A', 'D', 'D', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15679 */ 'A', 'N', 'D', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15691 */ 'R', 'E', 'P', 'L', 'A', 'C', 'E', '_', 'L', 'A', 'N', 'E', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15712 */ 'A', 'L', 'L', 'T', 'R', 'U', 'E', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15728 */ 'A', 'N', 'Y', 'T', 'R', 'U', 'E', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15744 */ 'N', 'E', 'G', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15756 */ 'S', 'H', 'L', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15768 */ 'C', 'A', 'L', 'L', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15781 */ 'M', 'U', 'L', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15793 */ 'E', 'Q', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15804 */ 'X', 'O', 'R', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15816 */ 'G', 'E', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15829 */ 'L', 'E', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15842 */ 'S', 'H', 'R', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15856 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15874 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15892 */ 'G', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15905 */ 'L', 'T', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15918 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'S', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15935 */ 'S', 'P', 'L', 'A', 'T', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15949 */ 'B', 'I', 'T', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15967 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 15990 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16007 */ 'A', 'N', 'D', 'N', 'O', 'T', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16022 */ 'G', 'E', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16035 */ 'L', 'E', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16048 */ 'S', 'H', 'R', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16062 */ 'S', 'U', 'B', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16080 */ 'A', 'D', 'D', '_', 'S', 'A', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16098 */ 'G', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16111 */ 'L', 'T', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16124 */ 'N', 'A', 'R', 'R', 'O', 'W', '_', 'U', '_', 'v', '1', '6', 'i', '8', '_', 'S', 0,
  /* 16141 */ 'L', 'O', 'A', 'D', '_', 'S', 'P', 'L', 'A', 'T', '_', 'v', '1', '6', 'x', '8', '_', 'S', 0,
  /* 16160 */ 'C', 'A', 'L', 'L', '_', 'V', 'O', 'I', 'D', '_', 'S', 0,
  /* 16172 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'V', 'O', 'I', 'D', '_', 'S', 0,
  /* 16194 */ 'E', 'N', 'D', '_', 'S', 0,
  /* 16200 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'F', 'E', 'N', 'C', 'E', '_', 'S', 0,
  /* 16215 */ 'C', 'O', 'M', 'P', 'I', 'L', 'E', 'R', '_', 'F', 'E', 'N', 'C', 'E', '_', 'S', 0,
  /* 16232 */ 'U', 'N', 'R', 'E', 'A', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'S', 0,
  /* 16246 */ 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'S', 0,
  /* 16256 */ 'S', 'W', 'I', 'Z', 'Z', 'L', 'E', '_', 'S', 0,
  /* 16266 */ 'E', 'L', 'S', 'E', '_', 'S', 0,
  /* 16273 */ 'L', 'O', 'C', 'A', 'L', '_', 'T', 'E', 'E', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16292 */ 'D', 'R', 'O', 'P', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16306 */ 'S', 'E', 'L', 'E', 'C', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16322 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'G', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16342 */ 'L', 'O', 'C', 'A', 'L', '_', 'G', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16361 */ 'G', 'L', 'O', 'B', 'A', 'L', '_', 'S', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16381 */ 'L', 'O', 'C', 'A', 'L', '_', 'S', 'E', 'T', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16400 */ 'C', 'O', 'P', 'Y', '_', 'E', 'X', 'N', 'R', 'E', 'F', '_', 'S', 0,
  /* 16414 */ 'E', 'N', 'D', '_', 'I', 'F', '_', 'S', 0,
  /* 16423 */ 'B', 'R', '_', 'I', 'F', '_', 'S', 0,
  /* 16431 */ 'R', 'E', 'T', 'H', 'R', 'O', 'W', '_', 'I', 'N', '_', 'C', 'A', 'T', 'C', 'H', '_', 'S', 0,
  /* 16450 */ 'E', 'N', 'D', '_', 'B', 'L', 'O', 'C', 'K', '_', 'S', 0,
  /* 16462 */ 'R', 'E', 'T', '_', 'C', 'A', 'L', 'L', '_', 'S', 0,
  /* 16473 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'F', 'I', 'L', 'L', '_', 'S', 0,
  /* 16487 */ 'E', 'N', 'D', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'S', 0,
  /* 16502 */ 'F', 'A', 'L', 'L', 'T', 'H', 'R', 'O', 'U', 'G', 'H', '_', 'R', 'E', 'T', 'U', 'R', 'N', '_', 'S', 0,
  /* 16523 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', '_', 'S', 0,
  /* 16542 */ 'B', 'R', '_', 'O', 'N', '_', 'E', 'X', 'N', '_', 'S', 0,
  /* 16554 */ 'N', 'O', 'P', '_', 'S', 0,
  /* 16560 */ 'E', 'N', 'D', '_', 'L', 'O', 'O', 'P', '_', 'S', 0,
  /* 16571 */ 'D', 'A', 'T', 'A', '_', 'D', 'R', 'O', 'P', '_', 'S', 0,
  /* 16583 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', '_', 'S', 0,
  /* 16600 */ 'B', 'R', '_', 'S', 0,
  /* 16605 */ 'B', 'R', '_', 'U', 'N', 'L', 'E', 'S', 'S', '_', 'S', 0,
  /* 16617 */ 'P', 'R', 'E', 'T', '_', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'S', 0,
  /* 16638 */ 'C', 'A', 'T', 'C', 'H', 'R', 'E', 'T', '_', 'S', 0,
  /* 16649 */ 'C', 'L', 'E', 'A', 'N', 'U', 'P', 'R', 'E', 'T', '_', 'S', 0,
  /* 16662 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'I', 'N', 'I', 'T', '_', 'S', 0,
  /* 16676 */ 'R', 'E', 'T', 'H', 'R', 'O', 'W', '_', 'S', 0,
  /* 16686 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'N', 'O', 'T', 'I', 'F', 'Y', '_', 'S', 0,
  /* 16702 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'C', 'O', 'P', 'Y', '_', 'S', 0,
  /* 16716 */ 'E', 'N', 'D', '_', 'T', 'R', 'Y', '_', 'S', 0,
  /* 16726 */ 'C', 'A', 'L', 'L', '_', 'e', 'x', 'n', 'r', 'e', 'f', '_', 'S', 0,
  /* 16740 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'e', 'x', 'n', 'r', 'e', 'f', '_', 'S', 0,
  /* 16764 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'e', 'x', 'n', 'r', 'e', 'f', '_', 'S', 0,
  /* 16782 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '8', 'i', '1', '6', '_', 's', '_', 'S', 0,
  /* 16805 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '1', '6', 'i', '8', '_', 's', '_', 'S', 0,
  /* 16828 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '8', 'i', '1', '6', '_', 'u', '_', 'S', 0,
  /* 16851 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '1', '6', 'i', '8', '_', 'u', '_', 'S', 0,
  /* 16874 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
  /* 16884 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
  /* 16893 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
  /* 16906 */ 'P', 'R', 'E', 'T', '_', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
  /* 16925 */ 'C', 'A', 'T', 'C', 'H', 'R', 'E', 'T', 0,
  /* 16934 */ 'C', 'L', 'E', 'A', 'N', 'U', 'P', 'R', 'E', 'T', 0,
  /* 16945 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
  /* 16959 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'I', 'N', 'I', 'T', 0,
  /* 16971 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
  /* 16995 */ 'G', '_', 'B', 'R', 'J', 'T', 0,
  /* 17002 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
  /* 17023 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
  /* 17043 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
  /* 17055 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
  /* 17066 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
  /* 17077 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
  /* 17088 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
  /* 17099 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0,
  /* 17107 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0,
  /* 17120 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
  /* 17130 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
  /* 17145 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
  /* 17154 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
  /* 17162 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
  /* 17172 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
  /* 17189 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
  /* 17197 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
  /* 17204 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
  /* 17213 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
  /* 17220 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
  /* 17227 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
  /* 17234 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
  /* 17241 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
  /* 17248 */ 'R', 'E', 'T', 'H', 'R', 'O', 'W', 0,
  /* 17256 */ 'G', '_', 'S', 'M', 'A', 'X', 0,
  /* 17263 */ 'G', '_', 'U', 'M', 'A', 'X', 0,
  /* 17270 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
  /* 17287 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
  /* 17303 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
  /* 17317 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'N', 'O', 'T', 'I', 'F', 'Y', 0,
  /* 17331 */ 'M', 'E', 'M', 'O', 'R', 'Y', '_', 'C', 'O', 'P', 'Y', 0,
  /* 17343 */ 'E', 'N', 'D', '_', 'T', 'R', 'Y', 0,
  /* 17351 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
  /* 17358 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
  /* 17365 */ 'C', 'A', 'L', 'L', '_', 'e', 'x', 'n', 'r', 'e', 'f', 0,
  /* 17377 */ 'P', 'C', 'A', 'L', 'L', '_', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', '_', 'e', 'x', 'n', 'r', 'e', 'f', 0,
  /* 17399 */ 'A', 'R', 'G', 'U', 'M', 'E', 'N', 'T', '_', 'e', 'x', 'n', 'r', 'e', 'f', 0,
  /* 17415 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '8', 'i', '1', '6', '_', 's', 0,
  /* 17436 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '1', '6', 'i', '8', '_', 's', 0,
  /* 17457 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '8', 'i', '1', '6', '_', 'u', 0,
  /* 17478 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'L', 'A', 'N', 'E', '_', 'v', '1', '6', 'i', '8', '_', 'u', 0,
};

extern const unsigned WebAssemblyInstrNameIndices[] = {
    7654U, 7916U, 8295U, 8047U, 7716U, 7697U, 7725U, 7877U, 
    7514U, 7529U, 7356U, 7556U, 8517U, 7277U, 7706U, 7115U, 
    17338U, 7199U, 17130U, 7006U, 8157U, 7853U, 17077U, 7046U, 
    17066U, 7222U, 8256U, 8243U, 8321U, 16945U, 16971U, 7776U, 
    7832U, 7805U, 7742U, 6915U, 6694U, 7889U, 17227U, 17234U, 
    7902U, 7909U, 6984U, 8423U, 8401U, 7354U, 7652U, 17303U, 
    7287U, 16874U, 8461U, 17145U, 8478U, 8369U, 6764U, 8500U, 
    17088U, 8443U, 17162U, 6738U, 7028U, 6884U, 6828U, 6858U, 
    6869U, 6809U, 6839U, 7251U, 7235U, 8534U, 7570U, 7587U, 
    6921U, 6700U, 6990U, 6967U, 8428U, 8407U, 17287U, 8011U, 
    17270U, 7994U, 6898U, 6677U, 7092U, 7019U, 16893U, 6716U, 
    8574U, 17204U, 6756U, 17055U, 17043U, 17120U, 7611U, 17197U, 
    7543U, 17213U, 7762U, 8353U, 8346U, 8205U, 8198U, 16884U, 
    8133U, 7136U, 8117U, 7071U, 8125U, 7128U, 8109U, 7063U, 
    8149U, 8141U, 7644U, 7636U, 6891U, 6670U, 7882U, 6664U, 
    6802U, 17220U, 7895U, 17241U, 8283U, 2602U, 7604U, 2594U, 
    0U, 7507U, 17189U, 6728U, 7658U, 7667U, 8180U, 8189U, 
    8454U, 7968U, 7302U, 7948U, 7958U, 7144U, 7159U, 7926U, 
    7937U, 8174U, 7686U, 7980U, 17256U, 7987U, 17263U, 8290U, 
    16995U, 17023U, 17002U, 8384U, 17358U, 7336U, 17351U, 7318U, 
    8225U, 8166U, 7264U, 7768U, 8493U, 8027U, 17154U, 8360U, 
    17099U, 17107U, 17172U, 8308U, 7186U, 6785U, 16925U, 16638U, 
    16934U, 16649U, 7100U, 16215U, 7619U, 16431U, 253U, 8889U, 
    2870U, 11864U, 4708U, 13944U, 1930U, 10794U, 112U, 8718U, 
    2730U, 11694U, 696U, 9390U, 3355U, 12411U, 6414U, 15874U, 
    5664U, 15026U, 6594U, 16080U, 5864U, 15254U, 6237U, 15667U, 
    4592U, 13808U, 4956U, 14228U, 1814U, 10658U, 2178U, 11078U, 
    5467U, 14797U, 8082U, 16523U, 8268U, 16583U, 6276U, 15712U, 
    5014U, 14294U, 2236U, 11144U, 5506U, 14842U, 6531U, 16007U, 
    5179U, 14483U, 2464U, 11408U, 5781U, 15159U, 760U, 9460U, 
    3442U, 12506U, 6247U, 15679U, 4966U, 14240U, 2188U, 11090U, 
    5477U, 14809U, 6290U, 15728U, 5028U, 14310U, 2250U, 11160U, 
    5520U, 14858U, 17399U, 16764U, 2092U, 10982U, 4870U, 14132U, 
    2581U, 11543U, 5252U, 14566U, 6516U, 15990U, 4796U, 14046U, 
    5164U, 14466U, 2018U, 10896U, 2449U, 11391U, 5766U, 15142U, 
    7079U, 16200U, 1523U, 10323U, 4334U, 13510U, 4314U, 13488U, 
    1543U, 10345U, 4354U, 13532U, 665U, 9357U, 3324U, 12378U, 
    17317U, 16686U, 681U, 9375U, 3363U, 12421U, 745U, 9445U, 
    3450U, 12516U, 876U, 9592U, 3592U, 12674U, 1146U, 9892U, 
    3922U, 13040U, 601U, 9287U, 3260U, 12308U, 952U, 9674U, 
    3692U, 12782U, 1082U, 9822U, 3836U, 12946U, 3340U, 12396U, 
    3427U, 12491U, 3565U, 12645U, 3900U, 13016U, 3237U, 12283U, 
    3668U, 12756U, 3813U, 12921U, 704U, 9400U, 3386U, 12446U, 
    768U, 9470U, 3473U, 12541U, 903U, 9621U, 3619U, 12703U, 
    1168U, 9916U, 3944U, 13064U, 624U, 9312U, 3283U, 12333U, 
    976U, 9700U, 3716U, 12808U, 1105U, 9847U, 3859U, 12971U, 
    726U, 9424U, 3408U, 12470U, 790U, 9494U, 3495U, 12565U, 
    929U, 9649U, 3645U, 12731U, 1189U, 9939U, 3965U, 13087U, 
    646U, 9336U, 3305U, 12357U, 999U, 9725U, 3739U, 12833U, 
    1127U, 9871U, 3881U, 12995U, 564U, 9246U, 3200U, 12242U, 
    3181U, 12221U, 583U, 9267U, 3219U, 12263U, 843U, 9555U, 
    3548U, 12626U, 1486U, 10280U, 4277U, 13445U, 6479U, 15949U, 
    4741U, 13983U, 5127U, 14425U, 1963U, 10833U, 2412U, 11350U, 
    5729U, 15101U, 7680U, 16454U, 8292U, 7501U, 16423U, 8099U, 
    16542U, 16600U, 823U, 9531U, 3528U, 12602U, 8564U, 16605U, 
    6948U, 16173U, 17378U, 16741U, 2074U, 10962U, 4852U, 14112U, 
    2563U, 11523U, 5234U, 14546U, 6496U, 15968U, 4758U, 14002U, 
    5144U, 14444U, 1980U, 10852U, 2429U, 11369U, 5746U, 15120U, 
    6937U, 16160U, 17365U, 16726U, 2064U, 10950U, 4842U, 14100U, 
    2553U, 11511U, 5224U, 14534U, 6324U, 15768U, 4668U, 13896U, 
    5062U, 14350U, 1890U, 10746U, 2284U, 11200U, 5554U, 14898U, 
    7630U, 16442U, 189U, 8811U, 2806U, 11786U, 1706U, 10534U, 
    4484U, 13684U, 497U, 9167U, 3114U, 12142U, 1513U, 10311U, 
    4304U, 13476U, 6210U, 15636U, 4554U, 13764U, 4929U, 14197U, 
    1776U, 10614U, 2151U, 11047U, 5440U, 14766U, 206U, 8832U, 
    2823U, 11807U, 7482U, 16400U, 555U, 9235U, 3172U, 12210U, 
    1697U, 10523U, 4475U, 13673U, 6042U, 15458U, 1722U, 10554U, 
    4500U, 13704U, 8233U, 16571U, 539U, 9215U, 3156U, 12190U, 
    1387U, 10167U, 4178U, 13332U, 1671U, 10493U, 4465U, 13661U, 
    4822U, 14076U, 2044U, 10926U, 7386U, 16292U, 227U, 8857U, 
    2844U, 11832U, 1066U, 9802U, 3797U, 12901U, 5970U, 15376U, 
    7259U, 16266U, 7015U, 7676U, 16450U, 8034U, 16487U, 7494U, 
    16414U, 8216U, 16560U, 16194U, 17343U, 16716U, 1714U, 10544U, 
    4492U, 13694U, 236U, 8868U, 2853U, 11843U, 1075U, 9813U, 
    3806U, 12912U, 6345U, 15793U, 4699U, 13933U, 1921U, 10783U, 
    2305U, 11225U, 5575U, 14923U, 1044U, 9778U, 17436U, 16805U, 
    17478U, 16851U, 4639U, 13863U, 4995U, 14273U, 1861U, 10713U, 
    2217U, 11123U, 17415U, 16782U, 17457U, 16828U, 1351U, 10127U, 
    4142U, 13292U, 1635U, 10453U, 4429U, 13621U, 2783U, 11759U, 
    1437U, 10225U, 1369U, 10147U, 4160U, 13312U, 1653U, 10473U, 
    4447U, 13641U, 165U, 8783U, 4228U, 13390U, 8063U, 16502U, 
    243U, 8877U, 2860U, 11852U, 9U, 8601U, 2627U, 11577U, 
    47U, 8643U, 2665U, 11619U, 28U, 8622U, 2646U, 11598U, 
    66U, 8664U, 2684U, 11640U, 134U, 8744U, 2752U, 11720U, 
    1295U, 10059U, 4086U, 13224U, 6364U, 15816U, 2344U, 11270U, 
    5614U, 14968U, 1579U, 10385U, 4373U, 13553U, 6544U, 16022U, 
    2497U, 11445U, 5814U, 15196U, 4602U, 13820U, 1824U, 10670U, 
    7412U, 16322U, 384U, 9036U, 3001U, 12011U, 1408U, 10192U, 
    4199U, 13357U, 5980U, 15388U, 7447U, 16361U, 433U, 9091U, 
    3050U, 12066U, 1457U, 10247U, 4248U, 13412U, 6011U, 15423U, 
    462U, 9124U, 3079U, 12099U, 1333U, 10105U, 4124U, 13270U, 
    6430U, 15892U, 2378U, 11310U, 5680U, 15044U, 1617U, 10431U, 
    4411U, 13599U, 6610U, 16098U, 2531U, 11485U, 5880U, 15272U, 
    4778U, 14024U, 2000U, 10874U, 1229U, 9985U, 1260U, 10020U, 
    413U, 9069U, 261U, 8899U, 2878U, 11874U, 293U, 8935U, 
    2910U, 11910U, 507U, 9179U, 3124U, 12154U, 333U, 8979U, 
    2950U, 11954U, 3784U, 12886U, 4037U, 13169U, 4005U, 13133U, 
    4068U, 13204U, 1278U, 10040U, 1562U, 10366U, 3030U, 12044U, 
    277U, 8917U, 2894U, 11892U, 313U, 8957U, 2930U, 11932U, 
    523U, 9197U, 3140U, 12172U, 353U, 9001U, 2970U, 11976U, 
    7498U, 16418U, 141U, 8753U, 2759U, 11729U, 1304U, 10070U, 
    4095U, 13235U, 6375U, 15829U, 2355U, 11283U, 5625U, 14981U, 
    1588U, 10396U, 4382U, 13564U, 6555U, 16035U, 2508U, 11458U, 
    5825U, 15209U, 4611U, 13831U, 1833U, 10681U, 1216U, 9970U, 
    4024U, 13154U, 1530U, 10330U, 4341U, 13517U, 3992U, 13118U, 
    4321U, 13495U, 1248U, 10006U, 4056U, 13190U, 1550U, 10352U, 
    4361U, 13539U, 5083U, 14375U, 2324U, 11248U, 5594U, 14946U, 
    5192U, 14498U, 2477U, 11423U, 5794U, 15174U, 103U, 8707U, 
    2721U, 11683U, 672U, 9364U, 3331U, 12385U, 6647U, 16141U, 
    5265U, 14581U, 2610U, 11558U, 5917U, 15315U, 5934U, 15334U, 
    7430U, 16342U, 399U, 9053U, 3016U, 12028U, 1423U, 10209U, 
    4214U, 13374U, 5996U, 15406U, 7465U, 16381U, 448U, 9108U, 
    3065U, 12083U, 1472U, 10264U, 4263U, 13429U, 6027U, 15441U, 
    7369U, 16273U, 120U, 8728U, 2738U, 11704U, 809U, 9515U, 
    3514U, 12586U, 5944U, 15346U, 8220U, 16564U, 469U, 9133U, 
    3086U, 12108U, 1342U, 10116U, 4133U, 13281U, 6441U, 15905U, 
    2389U, 11323U, 5691U, 15057U, 1626U, 10442U, 4420U, 13610U, 
    6621U, 16111U, 2542U, 11498U, 5891U, 15285U, 4787U, 14035U, 
    2009U, 10885U, 547U, 9225U, 3164U, 12200U, 4832U, 14088U, 
    2054U, 10938U, 17331U, 16702U, 7865U, 16473U, 1681U, 10505U, 
    16959U, 16662U, 860U, 9574U, 219U, 8847U, 2836U, 11822U, 
    4689U, 13921U, 1911U, 10771U, 198U, 8822U, 2815U, 11797U, 
    1036U, 9768U, 3776U, 12876U, 6335U, 15781U, 4679U, 13909U, 
    1901U, 10759U, 2295U, 11213U, 5565U, 14911U, 6452U, 15918U, 
    5702U, 15070U, 6632U, 16124U, 5902U, 15298U, 485U, 9153U, 
    3102U, 12128U, 181U, 8801U, 2798U, 11776U, 6304U, 15744U, 
    4658U, 13884U, 5042U, 14326U, 1880U, 10734U, 2264U, 11176U, 
    5534U, 14874U, 148U, 8762U, 2766U, 11738U, 836U, 9546U, 
    3541U, 12617U, 6267U, 15701U, 4630U, 13852U, 1852U, 10702U, 
    2208U, 11112U, 5497U, 14831U, 8212U, 16554U, 6534U, 16010U, 
    5182U, 14486U, 2467U, 11411U, 5784U, 15162U, 1098U, 9838U, 
    3829U, 12937U, 6355U, 15805U, 5074U, 14364U, 2315U, 11237U, 
    5585U, 14935U, 6947U, 16172U, 17377U, 16740U, 2073U, 10961U, 
    4851U, 14111U, 2562U, 11522U, 5233U, 14545U, 6495U, 15967U, 
    4757U, 14001U, 5143U, 14443U, 1979U, 10851U, 2428U, 11368U, 
    5745U, 15119U, 1502U, 10298U, 4293U, 13463U, 16906U, 16617U, 
    4571U, 13783U, 1793U, 10633U, 4718U, 13956U, 1940U, 10806U, 
    1313U, 10081U, 4104U, 13246U, 1597U, 10407U, 4391U, 13575U, 
    6257U, 15691U, 4620U, 13842U, 4976U, 14252U, 1842U, 10692U, 
    2198U, 11102U, 5487U, 14821U, 17248U, 16676U, 8075U, 16514U, 
    7796U, 16907U, 16618U, 16462U, 1027U, 9757U, 3767U, 12865U, 
    1207U, 9959U, 3983U, 13107U, 7398U, 16306U, 373U, 9023U, 
    2990U, 11998U, 1397U, 10179U, 4188U, 13344U, 1019U, 9747U, 
    3759U, 12855U, 6314U, 15756U, 5052U, 14338U, 2274U, 11188U, 
    5544U, 14886U, 1323U, 10093U, 4114U, 13258U, 6386U, 15842U, 
    5103U, 14397U, 2366U, 11296U, 5636U, 14994U, 1607U, 10419U, 
    4401U, 13587U, 6566U, 16048U, 5212U, 14520U, 2519U, 11471U, 
    5836U, 15222U, 7206U, 16246U, 6467U, 15935U, 4729U, 13969U, 
    5115U, 14411U, 1951U, 10819U, 2400U, 11336U, 5717U, 15087U, 
    476U, 9142U, 3093U, 12117U, 4811U, 14063U, 2033U, 10913U, 
    571U, 9253U, 3207U, 12249U, 3188U, 12228U, 590U, 9274U, 
    3226U, 12270U, 155U, 8771U, 2773U, 11747U, 850U, 9562U, 
    3555U, 12633U, 5959U, 15363U, 85U, 8685U, 2703U, 11661U, 
    616U, 9302U, 3252U, 12298U, 6398U, 15856U, 5648U, 15008U, 
    6578U, 16062U, 5848U, 15236U, 6227U, 15655U, 4582U, 13796U, 
    4946U, 14216U, 1804U, 10646U, 2168U, 11066U, 5457U, 14785U, 
    7214U, 16256U, 7375U, 16279U, 126U, 8734U, 2744U, 11710U, 
    815U, 9521U, 3520U, 12592U, 5950U, 15352U, 17250U, 16678U, 
    93U, 8695U, 2711U, 11671U, 17347U, 16720U, 7174U, 16232U, 
    1097U, 9837U, 3828U, 12936U, 6354U, 15804U, 5073U, 14363U, 
    2314U, 11236U, 5584U, 14934U, 4508U, 13714U, 1730U, 10564U, 
    4531U, 13739U, 1753U, 10589U, 5282U, 14600U, 6052U, 15470U, 
    5359U, 14681U, 6129U, 15551U, 5321U, 14641U, 6091U, 15511U, 
    5400U, 14724U, 6170U, 15594U, 4883U, 14147U, 2105U, 10997U, 
    4906U, 14172U, 2128U, 11022U, 
};

static inline void InitWebAssemblyMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(WebAssemblyInsts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, 1316);
}

} // end namespace llvm
#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER
namespace llvm {
struct WebAssemblyGenInstrInfo : public TargetInstrInfo {
  explicit WebAssemblyGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
  ~WebAssemblyGenInstrInfo() override = default;

};
} // end namespace llvm
#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS

#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR
namespace llvm {
extern const MCInstrDesc WebAssemblyInsts[];
extern const unsigned WebAssemblyInstrNameIndices[];
extern const char WebAssemblyInstrNameData[];
WebAssemblyGenInstrInfo::WebAssemblyGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(WebAssemblyInsts, WebAssemblyInstrNameIndices, WebAssemblyInstrNameData, 1316);
}
} // end namespace llvm
#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
namespace WebAssembly {
namespace OpName {
enum {
  addr = 3,
  count = 4,
  dst = 0,
  exp = 6,
  new_ = 7,
  off = 2,
  p2align = 1,
  timeout = 8,
  val = 5,
  vec = 9,
OPERAND_LAST
};
} // end namespace OpName
} // end namespace WebAssembly
} // end namespace llvm
#endif //GET_INSTRINFO_OPERAND_ENUM

#ifdef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_NAMED_OPS
namespace llvm {
namespace WebAssembly {
LLVM_READONLY
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
  static const int16_t OperandMap [][10] = {
{0, 1, 2, 3, -1, -1, -1, -1, -1, -1, },
{0, 1, 2, 3, 4, -1, -1, -1, -1, -1, },
{0, 1, 2, 3, -1, 4, -1, -1, -1, -1, },
{0, 1, 2, 3, -1, -1, 4, 5, -1, -1, },
{0, 1, 2, 3, -1, -1, 4, -1, 5, -1, },
{-1, 0, 1, -1, -1, -1, -1, -1, -1, -1, },
{-1, 0, 1, 2, -1, 3, -1, -1, -1, -1, },
{-1, 0, 1, 2, -1, -1, -1, -1, -1, 3, },
};
  switch(Opcode) {
  case WebAssembly::ATOMIC_LOAD16_U_I32:
  case WebAssembly::ATOMIC_LOAD16_U_I64:
  case WebAssembly::ATOMIC_LOAD32_U_I64:
  case WebAssembly::ATOMIC_LOAD8_U_I32:
  case WebAssembly::ATOMIC_LOAD8_U_I64:
  case WebAssembly::ATOMIC_LOAD_I32:
  case WebAssembly::ATOMIC_LOAD_I64:
  case WebAssembly::LOAD16_S_I32:
  case WebAssembly::LOAD16_S_I64:
  case WebAssembly::LOAD16_U_I32:
  case WebAssembly::LOAD16_U_I64:
  case WebAssembly::LOAD32_S_I64:
  case WebAssembly::LOAD32_U_I64:
  case WebAssembly::LOAD8_S_I32:
  case WebAssembly::LOAD8_S_I64:
  case WebAssembly::LOAD8_U_I32:
  case WebAssembly::LOAD8_U_I64:
  case WebAssembly::LOAD_EXTEND_S_v2i64:
  case WebAssembly::LOAD_EXTEND_S_v4i32:
  case WebAssembly::LOAD_EXTEND_S_v8i16:
  case WebAssembly::LOAD_EXTEND_U_v2i64:
  case WebAssembly::LOAD_EXTEND_U_v4i32:
  case WebAssembly::LOAD_EXTEND_U_v8i16:
  case WebAssembly::LOAD_F32:
  case WebAssembly::LOAD_F64:
  case WebAssembly::LOAD_I32:
  case WebAssembly::LOAD_I64:
  case WebAssembly::LOAD_SPLAT_v16x8:
  case WebAssembly::LOAD_SPLAT_v32x4:
  case WebAssembly::LOAD_SPLAT_v64x2:
  case WebAssembly::LOAD_SPLAT_v8x16:
  case WebAssembly::LOAD_V128:
    return OperandMap[0][NamedIdx];
  case WebAssembly::ATOMIC_NOTIFY:
    return OperandMap[1][NamedIdx];
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32:
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64:
  case WebAssembly::ATOMIC_RMW16_U_AND_I32:
  case WebAssembly::ATOMIC_RMW16_U_AND_I64:
  case WebAssembly::ATOMIC_RMW16_U_OR_I32:
  case WebAssembly::ATOMIC_RMW16_U_OR_I64:
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32:
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64:
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32:
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64:
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32:
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64:
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64:
  case WebAssembly::ATOMIC_RMW32_U_AND_I64:
  case WebAssembly::ATOMIC_RMW32_U_OR_I64:
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64:
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64:
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64:
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32:
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64:
  case WebAssembly::ATOMIC_RMW8_U_AND_I32:
  case WebAssembly::ATOMIC_RMW8_U_AND_I64:
  case WebAssembly::ATOMIC_RMW8_U_OR_I32:
  case WebAssembly::ATOMIC_RMW8_U_OR_I64:
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32:
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64:
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32:
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64:
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32:
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64:
  case WebAssembly::ATOMIC_RMW_ADD_I32:
  case WebAssembly::ATOMIC_RMW_ADD_I64:
  case WebAssembly::ATOMIC_RMW_AND_I32:
  case WebAssembly::ATOMIC_RMW_AND_I64:
  case WebAssembly::ATOMIC_RMW_OR_I32:
  case WebAssembly::ATOMIC_RMW_OR_I64:
  case WebAssembly::ATOMIC_RMW_SUB_I32:
  case WebAssembly::ATOMIC_RMW_SUB_I64:
  case WebAssembly::ATOMIC_RMW_XCHG_I32:
  case WebAssembly::ATOMIC_RMW_XCHG_I64:
  case WebAssembly::ATOMIC_RMW_XOR_I32:
  case WebAssembly::ATOMIC_RMW_XOR_I64:
    return OperandMap[2][NamedIdx];
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32:
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64:
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64:
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32:
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64:
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32:
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64:
    return OperandMap[3][NamedIdx];
  case WebAssembly::ATOMIC_WAIT_I32:
  case WebAssembly::ATOMIC_WAIT_I64:
    return OperandMap[4][NamedIdx];
  case WebAssembly::ATOMIC_LOAD16_U_I32_S:
  case WebAssembly::ATOMIC_LOAD16_U_I64_S:
  case WebAssembly::ATOMIC_LOAD32_U_I64_S:
  case WebAssembly::ATOMIC_LOAD8_U_I32_S:
  case WebAssembly::ATOMIC_LOAD8_U_I64_S:
  case WebAssembly::ATOMIC_LOAD_I32_S:
  case WebAssembly::ATOMIC_LOAD_I64_S:
  case WebAssembly::ATOMIC_NOTIFY_S:
  case WebAssembly::ATOMIC_RMW16_U_ADD_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_ADD_I64_S:
  case WebAssembly::ATOMIC_RMW16_U_AND_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_AND_I64_S:
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S:
  case WebAssembly::ATOMIC_RMW16_U_OR_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_OR_I64_S:
  case WebAssembly::ATOMIC_RMW16_U_SUB_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_SUB_I64_S:
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S:
  case WebAssembly::ATOMIC_RMW16_U_XOR_I32_S:
  case WebAssembly::ATOMIC_RMW16_U_XOR_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_ADD_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_AND_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_OR_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_SUB_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S:
  case WebAssembly::ATOMIC_RMW32_U_XOR_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_ADD_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_ADD_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_AND_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_AND_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_OR_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_OR_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_SUB_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_SUB_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S:
  case WebAssembly::ATOMIC_RMW8_U_XOR_I32_S:
  case WebAssembly::ATOMIC_RMW8_U_XOR_I64_S:
  case WebAssembly::ATOMIC_RMW_ADD_I32_S:
  case WebAssembly::ATOMIC_RMW_ADD_I64_S:
  case WebAssembly::ATOMIC_RMW_AND_I32_S:
  case WebAssembly::ATOMIC_RMW_AND_I64_S:
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S:
  case WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S:
  case WebAssembly::ATOMIC_RMW_OR_I32_S:
  case WebAssembly::ATOMIC_RMW_OR_I64_S:
  case WebAssembly::ATOMIC_RMW_SUB_I32_S:
  case WebAssembly::ATOMIC_RMW_SUB_I64_S:
  case WebAssembly::ATOMIC_RMW_XCHG_I32_S:
  case WebAssembly::ATOMIC_RMW_XCHG_I64_S:
  case WebAssembly::ATOMIC_RMW_XOR_I32_S:
  case WebAssembly::ATOMIC_RMW_XOR_I64_S:
  case WebAssembly::ATOMIC_STORE16_I32_S:
  case WebAssembly::ATOMIC_STORE16_I64_S:
  case WebAssembly::ATOMIC_STORE32_I64_S:
  case WebAssembly::ATOMIC_STORE8_I32_S:
  case WebAssembly::ATOMIC_STORE8_I64_S:
  case WebAssembly::ATOMIC_STORE_I32_S:
  case WebAssembly::ATOMIC_STORE_I64_S:
  case WebAssembly::ATOMIC_WAIT_I32_S:
  case WebAssembly::ATOMIC_WAIT_I64_S:
  case WebAssembly::LOAD16_S_I32_S:
  case WebAssembly::LOAD16_S_I64_S:
  case WebAssembly::LOAD16_U_I32_S:
  case WebAssembly::LOAD16_U_I64_S:
  case WebAssembly::LOAD32_S_I64_S:
  case WebAssembly::LOAD32_U_I64_S:
  case WebAssembly::LOAD8_S_I32_S:
  case WebAssembly::LOAD8_S_I64_S:
  case WebAssembly::LOAD8_U_I32_S:
  case WebAssembly::LOAD8_U_I64_S:
  case WebAssembly::LOAD_EXTEND_S_v2i64_S:
  case WebAssembly::LOAD_EXTEND_S_v4i32_S:
  case WebAssembly::LOAD_EXTEND_S_v8i16_S:
  case WebAssembly::LOAD_EXTEND_U_v2i64_S:
  case WebAssembly::LOAD_EXTEND_U_v4i32_S:
  case WebAssembly::LOAD_EXTEND_U_v8i16_S:
  case WebAssembly::LOAD_F32_S:
  case WebAssembly::LOAD_F64_S:
  case WebAssembly::LOAD_I32_S:
  case WebAssembly::LOAD_I64_S:
  case WebAssembly::LOAD_SPLAT_v16x8_S:
  case WebAssembly::LOAD_SPLAT_v32x4_S:
  case WebAssembly::LOAD_SPLAT_v64x2_S:
  case WebAssembly::LOAD_SPLAT_v8x16_S:
  case WebAssembly::LOAD_V128_S:
  case WebAssembly::STORE16_I32_S:
  case WebAssembly::STORE16_I64_S:
  case WebAssembly::STORE32_I64_S:
  case WebAssembly::STORE8_I32_S:
  case WebAssembly::STORE8_I64_S:
  case WebAssembly::STORE_F32_S:
  case WebAssembly::STORE_F64_S:
  case WebAssembly::STORE_I32_S:
  case WebAssembly::STORE_I64_S:
  case WebAssembly::STORE_V128_S:
    return OperandMap[5][NamedIdx];
  case WebAssembly::ATOMIC_STORE16_I32:
  case WebAssembly::ATOMIC_STORE16_I64:
  case WebAssembly::ATOMIC_STORE32_I64:
  case WebAssembly::ATOMIC_STORE8_I32:
  case WebAssembly::ATOMIC_STORE8_I64:
  case WebAssembly::ATOMIC_STORE_I32:
  case WebAssembly::ATOMIC_STORE_I64:
  case WebAssembly::STORE16_I32:
  case WebAssembly::STORE16_I64:
  case WebAssembly::STORE32_I64:
  case WebAssembly::STORE8_I32:
  case WebAssembly::STORE8_I64:
  case WebAssembly::STORE_F32:
  case WebAssembly::STORE_F64:
  case WebAssembly::STORE_I32:
  case WebAssembly::STORE_I64:
    return OperandMap[6][NamedIdx];
  case WebAssembly::STORE_V128:
    return OperandMap[7][NamedIdx];
    default: return -1;
  }
}
} // end namespace WebAssembly
} // end namespace llvm
#endif //GET_INSTRINFO_NAMED_OPS

#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
namespace llvm {
namespace WebAssembly {
namespace OpTypes {
enum OperandType {
  P2Align = 0,
  Signature = 1,
  TypeIndex = 2,
  bb_op = 3,
  brlist = 4,
  event_op = 5,
  f32imm = 6,
  f32imm_op = 7,
  f64imm = 8,
  f64imm_op = 9,
  function32_op = 10,
  global_op = 11,
  i16imm = 12,
  i1imm = 13,
  i32imm = 14,
  i32imm_op = 15,
  i64imm = 16,
  i64imm_op = 17,
  i8imm = 18,
  local_op = 19,
  offset32_op = 20,
  ptype0 = 21,
  ptype1 = 22,
  ptype2 = 23,
  ptype3 = 24,
  ptype4 = 25,
  ptype5 = 26,
  type0 = 27,
  type1 = 28,
  type2 = 29,
  type3 = 30,
  type4 = 31,
  type5 = 32,
  untyped_imm_0 = 33,
  vec_i16imm_op = 34,
  vec_i32imm_op = 35,
  vec_i64imm_op = 36,
  vec_i8imm_op = 37,
  EXNREF = 38,
  F32 = 39,
  F64 = 40,
  I32 = 41,
  I64 = 42,
  V128 = 43,
  OPERAND_TYPE_LIST_END
};
} // end namespace OpTypes
} // end namespace WebAssembly
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM

#ifdef GET_INSTRINFO_OPERAND_TYPE
#undef GET_INSTRINFO_OPERAND_TYPE
namespace llvm {
namespace WebAssembly {
LLVM_READONLY
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
  const int Offsets[] = {
    0,
    1,
    1,
    1,
    2,
    3,
    4,
    5,
    5,
    8,
    12,
    13,
    17,
    20,
    20,
    21,
    23,
    25,
    25,
    26,
    27,
    29,
    29,
    35,
    36,
    36,
    38,
    39,
    39,
    39,
    39,
    39,
    39,
    41,
    44,
    44,
    47,
    50,
    53,
    56,
    59,
    62,
    65,
    68,
    71,
    74,
    75,
    76,
    78,
    80,
    83,
    85,
    89,
    91,
    93,
    95,
    97,
    99,
    101,
    103,
    105,
    107,
    109,
    111,
    113,
    118,
    123,
    128,
    130,
    135,
    140,
    144,
    147,
    150,
    153,
    156,
    159,
    162,
    165,
    168,
    171,
    174,
    177,
    180,
    183,
    185,
    187,
    188,
    189,
    190,
    192,
    194,
    196,
    198,
    199,
    202,
    204,
    207,
    209,
    212,
    215,
    218,
    222,
    226,
    230,
    234,
    239,
    243,
    248,
    252,
    257,
    261,
    266,
    270,
    274,
    277,
    280,
    283,
    286,
    289,
    293,
    297,
    300,
    303,
    306,
    308,
    310,
    312,
    314,
    316,
    318,
    320,
    322,
    324,
    326,
    328,
    330,
    332,
    335,
    337,
    340,
    343,
    346,
    349,
    352,
    355,
    358,
    361,
    364,
    367,
    370,
    373,
    374,
    377,
    381,
    384,
    388,
    390,
    392,
    394,
    396,
    398,
    400,
    402,
    404,
    406,
    408,
    410,
    412,
    414,
    416,
    418,
    420,
    422,
    425,
    427,
    429,
    429,
    429,
    429,
    429,
    429,
    429,
    431,
    431,
    433,
    433,
    435,
    435,
    437,
    437,
    440,
    440,
    443,
    443,
    446,
    446,
    449,
    449,
    452,
    452,
    455,
    455,
    458,
    458,
    461,
    461,
    464,
    464,
    467,
    467,
    470,
    470,
    473,
    473,
    476,
    476,
    479,
    479,
    481,
    483,
    485,
    487,
    489,
    489,
    491,
    491,
    493,
    493,
    495,
    495,
    498,
    498,
    501,
    501,
    504,
    504,
    507,
    507,
    510,
    510,
    513,
    513,
    516,
    516,
    519,
    519,
    522,
    522,
    525,
    525,
    527,
    527,
    529,
    529,
    531,
    531,
    533,
    533,
    535,
    536,
    538,
    539,
    541,
    542,
    544,
    545,
    547,
    548,
    550,
    551,
    553,
    554,
    556,
    557,
    559,
    560,
    562,
    563,
    565,
    566,
    567,
    568,
    572,
    574,
    578,
    580,
    584,
    586,
    590,
    592,
    596,
    598,
    602,
    604,
    608,
    610,
    615,
    617,
    622,
    624,
    629,
    631,
    636,
    638,
    643,
    645,
    651,
    653,
    659,
    661,
    666,
    668,
    673,
    675,
    680,
    682,
    687,
    689,
    694,
    696,
    701,
    703,
    708,
    710,
    715,
    717,
    722,
    724,
    729,
    731,
    737,
    739,
    744,
    746,
    751,
    753,
    758,
    760,
    765,
    767,
    772,
    774,
    779,
    781,
    786,
    788,
    793,
    795,
    801,
    803,
    809,
    811,
    816,
    818,
    823,
    825,
    830,
    832,
    837,
    839,
    844,
    846,
    851,
    853,
    858,
    860,
    865,
    867,
    872,
    874,
    879,
    881,
    886,
    888,
    893,
    895,
    901,
    903,
    909,
    911,
    916,
    918,
    923,
    925,
    930,
    932,
    937,
    939,
    944,
    946,
    951,
    953,
    958,
    960,
    965,
    967,
    971,
    973,
    977,
    979,
    983,
    985,
    989,
    991,
    995,
    997,
    1001,
    1003,
    1007,
    1009,
    1015,
    1017,
    1023,
    1025,
    1029,
    1029,
    1033,
    1033,
    1037,
    1037,
    1041,
    1041,
    1045,
    1045,
    1049,
    1049,
    1050,
    1051,
    1052,
    1054,
    1055,
    1058,
    1060,
    1061,
    1062,
    1063,
    1064,
    1065,
    1067,
    1068,
    1070,
    1072,
    1075,
    1077,
    1080,
    1082,
    1085,
    1087,
    1090,
    1092,
    1095,
    1097,
    1100,
    1102,
    1105,
    1107,
    1110,
    1112,
    1115,
    1117,
    1120,
    1122,
    1125,
    1127,
    1128,
    1129,
    1131,
    1132,
    1134,
    1135,
    1137,
    1138,
    1140,
    1141,
    1143,
    1144,
    1146,
    1147,
    1149,
    1150,
    1152,
    1153,
    1155,
    1156,
    1158,
    1159,
    1161,
    1162,
    1163,
    1163,
    1165,
    1165,
    1167,
    1167,
    1169,
    1169,
    1171,
    1171,
    1173,
    1174,
    1176,
    1177,
    1179,
    1180,
    1182,
    1183,
    1200,
    1216,
    1219,
    1221,
    1224,
    1226,
    1231,
    1235,
    1240,
    1244,
    1253,
    1261,
    1264,
    1264,
    1267,
    1267,
    1269,
    1269,
    1271,
    1271,
    1273,
    1273,
    1275,
    1275,
    1277,
    1277,
    1279,
    1279,
    1281,
    1281,
    1283,
    1283,
    1284,
    1285,
    1288,
    1288,
    1291,
    1291,
    1294,
    1294,
    1297,
    1297,
    1300,
    1300,
    1303,
    1303,
    1306,
    1306,
    1309,
    1309,
    1310,
    1310,
    1311,
    1311,
    1312,
    1312,
    1313,
    1313,
    1314,
    1314,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1315,
    1317,
    1317,
    1319,
    1319,
    1322,
    1322,
    1325,
    1325,
    1328,
    1328,
    1331,
    1331,
    1334,
    1334,
    1337,
    1337,
    1340,
    1340,
    1343,
    1343,
    1346,
    1346,
    1347,
    1348,
    1351,
    1352,
    1355,
    1356,
    1359,
    1360,
    1363,
    1364,
    1367,
    1368,
    1371,
    1372,
    1375,
    1376,
    1379,
    1380,
    1382,
    1382,
    1384,
    1384,
    1386,
    1386,
    1388,
    1388,
    1390,
    1390,
    1392,
    1392,
    1394,
    1394,
    1396,
    1396,
    1398,
    1398,
    1400,
    1400,
    1402,
    1402,
    1404,
    1404,
    1404,
    1404,
    1406,
    1406,
    1408,
    1408,
    1410,
    1410,
    1412,
    1412,
    1414,
    1414,
    1416,
    1416,
    1418,
    1418,
    1420,
    1420,
    1422,
    1422,
    1424,
    1424,
    1427,
    1427,
    1430,
    1430,
    1433,
    1433,
    1436,
    1436,
    1439,
    1439,
    1442,
    1442,
    1445,
    1445,
    1448,
    1448,
    1451,
    1451,
    1454,
    1454,
    1457,
    1457,
    1460,
    1460,
    1463,
    1463,
    1466,
    1466,
    1468,
    1469,
    1471,
    1472,
    1474,
    1475,
    1477,
    1478,
    1480,
    1481,
    1483,
    1484,
    1486,
    1487,
    1489,
    1490,
    1492,
    1493,
    1495,
    1496,
    1498,
    1499,
    1501,
    1502,
    1505,
    1505,
    1508,
    1508,
    1511,
    1511,
    1514,
    1514,
    1517,
    1517,
    1520,
    1520,
    1523,
    1523,
    1526,
    1526,
    1529,
    1529,
    1532,
    1532,
    1535,
    1535,
    1538,
    1538,
    1541,
    1541,
    1544,
    1544,
    1546,
    1546,
    1548,
    1548,
    1550,
    1550,
    1552,
    1552,
    1554,
    1554,
    1556,
    1556,
    1558,
    1558,
    1560,
    1560,
    1562,
    1562,
    1564,
    1564,
    1566,
    1566,
    1568,
    1568,
    1570,
    1570,
    1572,
    1572,
    1574,
    1574,
    1576,
    1576,
    1578,
    1578,
    1580,
    1580,
    1582,
    1582,
    1584,
    1584,
    1586,
    1586,
    1588,
    1588,
    1590,
    1590,
    1592,
    1592,
    1594,
    1594,
    1596,
    1596,
    1598,
    1599,
    1602,
    1602,
    1605,
    1605,
    1608,
    1608,
    1611,
    1611,
    1614,
    1614,
    1617,
    1617,
    1620,
    1620,
    1623,
    1623,
    1626,
    1626,
    1629,
    1629,
    1632,
    1632,
    1635,
    1635,
    1638,
    1638,
    1641,
    1641,
    1645,
    1647,
    1651,
    1653,
    1657,
    1659,
    1663,
    1665,
    1669,
    1671,
    1675,
    1677,
    1681,
    1683,
    1687,
    1689,
    1693,
    1695,
    1699,
    1701,
    1705,
    1707,
    1711,
    1713,
    1717,
    1719,
    1723,
    1725,
    1729,
    1731,
    1735,
    1737,
    1741,
    1743,
    1747,
    1749,
    1753,
    1755,
    1759,
    1761,
    1765,
    1767,
    1771,
    1773,
    1777,
    1779,
    1783,
    1785,
    1789,
    1791,
    1793,
    1794,
    1796,
    1797,
    1799,
    1800,
    1802,
    1803,
    1805,
    1806,
    1808,
    1809,
    1811,
    1812,
    1814,
    1815,
    1817,
    1818,
    1820,
    1821,
    1823,
    1824,
    1826,
    1827,
    1830,
    1831,
    1834,
    1835,
    1838,
    1839,
    1842,
    1843,
    1846,
    1847,
    1850,
    1851,
    1852,
    1853,
    1856,
    1856,
    1859,
    1859,
    1862,
    1862,
    1865,
    1865,
    1868,
    1868,
    1871,
    1871,
    1874,
    1874,
    1877,
    1877,
    1880,
    1880,
    1883,
    1883,
    1886,
    1886,
    1889,
    1889,
    1892,
    1892,
    1895,
    1895,
    1898,
    1898,
    1901,
    1901,
    1904,
    1904,
    1907,
    1907,
    1912,
    1914,
    1918,
    1919,
    1922,
    1923,
    1928,
    1930,
    1932,
    1933,
    1936,
    1936,
    1939,
    1939,
    1942,
    1942,
    1945,
    1945,
    1948,
    1948,
    1951,
    1951,
    1954,
    1954,
    1957,
    1957,
    1960,
    1960,
    1963,
    1963,
    1966,
    1966,
    1969,
    1969,
    1972,
    1972,
    1975,
    1975,
    1978,
    1978,
    1981,
    1981,
    1984,
    1984,
    1986,
    1986,
    1988,
    1988,
    1990,
    1990,
    1992,
    1992,
    1994,
    1994,
    1996,
    1996,
    1998,
    1998,
    2000,
    2000,
    2002,
    2002,
    2004,
    2004,
    2007,
    2007,
    2010,
    2010,
    2013,
    2013,
    2016,
    2016,
    2019,
    2019,
    2022,
    2022,
    2025,
    2025,
    2028,
    2028,
    2031,
    2031,
    2031,
    2031,
    2033,
    2033,
    2035,
    2035,
    2037,
    2037,
    2039,
    2039,
    2042,
    2042,
    2045,
    2045,
    2048,
    2048,
    2051,
    2051,
    2054,
    2054,
    2057,
    2057,
    2058,
    2059,
    2061,
    2062,
    2064,
    2065,
    2067,
    2068,
    2070,
    2071,
    2073,
    2074,
    2076,
    2077,
    2079,
    2080,
    2082,
    2083,
    2085,
    2086,
    2088,
    2089,
    2091,
    2092,
    2094,
    2094,
    2096,
    2096,
    2097,
    2098,
    2102,
    2102,
    2106,
    2106,
    2110,
    2110,
    2114,
    2114,
    2117,
    2117,
    2120,
    2120,
    2123,
    2123,
    2126,
    2126,
    2130,
    2131,
    2135,
    2136,
    2140,
    2141,
    2145,
    2146,
    2150,
    2151,
    2155,
    2156,
    2157,
    2157,
    2157,
    2157,
    2158,
    2160,
    2162,
    2163,
    2166,
    2166,
    2169,
    2169,
    2172,
    2172,
    2175,
    2175,
    2179,
    2179,
    2183,
    2183,
    2187,
    2187,
    2191,
    2191,
    2195,
    2195,
    2198,
    2198,
    2201,
    2201,
    2204,
    2204,
    2207,
    2207,
    2210,
    2210,
    2213,
    2213,
    2216,
    2216,
    2219,
    2219,
    2222,
    2222,
    2225,
    2225,
    2228,
    2228,
    2231,
    2231,
    2234,
    2234,
    2237,
    2237,
    2240,
    2240,
    2243,
    2243,
    2246,
    2246,
    2249,
    2249,
    2268,
    2284,
    2286,
    2286,
    2288,
    2288,
    2290,
    2290,
    2292,
    2292,
    2294,
    2294,
    2296,
    2296,
    2298,
    2298,
    2300,
    2300,
    2302,
    2302,
    2304,
    2304,
    2308,
    2310,
    2314,
    2316,
    2320,
    2322,
    2326,
    2328,
    2332,
    2334,
    2338,
    2340,
    2344,
    2346,
    2350,
    2352,
    2356,
    2358,
    2362,
    2364,
    2367,
    2367,
    2370,
    2370,
    2373,
    2373,
    2376,
    2376,
    2379,
    2379,
    2382,
    2382,
    2385,
    2385,
    2388,
    2388,
    2391,
    2391,
    2394,
    2394,
    2397,
    2397,
    2400,
    2400,
    2403,
    2403,
    2406,
    2406,
    2409,
    2409,
    2412,
    2412,
    2415,
    2415,
    2418,
    2418,
    2421,
    2421,
    2424,
    2424,
    2427,
    2427,
    2428,
    2429,
    2431,
    2431,
    2433,
    2433,
    2434,
    2435,
    2435,
    2435,
    2438,
    2438,
    2441,
    2441,
    2444,
    2444,
    2447,
    2447,
    2450,
    2450,
    2453,
    2453,
    2455,
    2455,
    2457,
    2457,
    2459,
    2459,
    2461,
    2461,
    2463,
    2463,
    2465,
    2465,
    2467,
    2467,
    2469,
    2469,
    2471,
    2471,
    2473,
    2473,
    2475,
    2475,
    2477,
    2477,
    2479,
    2479,
    2481,
    2481,
    2483,
    2483,
    2485,
  };
  const int OpcodeOperandTypes[] = {
    -1, 
    /**/
    /**/
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    /**/
    -1, -1, OpTypes::i32imm, 
    -1, -1, -1, OpTypes::i32imm, 
    -1, 
    -1, -1, -1, OpTypes::i32imm, 
    -1, -1, OpTypes::i32imm, 
    /**/
    -1, 
    -1, -1, 
    -1, -1, 
    /**/
    OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i64imm, OpTypes::i32imm, 
    /**/
    -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, 
    -1, 
    /**/
    -1, OpTypes::i32imm, 
    -1, 
    /**/
    /**/
    /**/
    /**/
    /**/
    -1, OpTypes::i8imm, 
    OpTypes::i16imm, -1, OpTypes::i32imm, 
    /**/
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, 
    OpTypes::type0, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 
    OpTypes::type0, OpTypes::ptype1, 
    OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::type0, -1, 
    OpTypes::type0, 
    -1, 
    -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
    OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, -1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, OpTypes::type0, 
    -1, 
    OpTypes::ptype0, -1, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, 
    OpTypes::type0, OpTypes::type1, OpTypes::type2, 
    OpTypes::type0, OpTypes::type1, OpTypes::type1, -1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type0, 
    OpTypes::type0, OpTypes::type1, 
    OpTypes::type0, -1, 
    OpTypes::type0, -1, 
    OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm, 
    OpTypes::bb_op, OpTypes::bb_op, 
    OpTypes::bb_op, OpTypes::bb_op, 
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::i32imm, OpTypes::i32imm, 
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::V128, 
    /**/
    OpTypes::EXNREF, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::F32, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::F64, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::I32, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::I64, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::V128, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::V128, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::V128, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::V128, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::V128, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::V128, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::i8imm, 
    OpTypes::i8imm, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::Signature, 
    OpTypes::Signature, 
    OpTypes::bb_op, 
    OpTypes::bb_op, OpTypes::I32, 
    OpTypes::bb_op, 
    OpTypes::bb_op, OpTypes::event_op, OpTypes::EXNREF, 
    OpTypes::bb_op, OpTypes::event_op, 
    OpTypes::bb_op, 
    OpTypes::I32, 
    OpTypes::brlist, 
    OpTypes::I64, 
    OpTypes::brlist, 
    OpTypes::bb_op, OpTypes::I32, 
    OpTypes::bb_op, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::EXNREF, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::F32, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::F64, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::I32, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::I64, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::V128, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::V128, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::V128, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::V128, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::V128, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::V128, OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::EXNREF, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::F32, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::F64, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::I32, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::I64, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::V128, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::V128, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::V128, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::V128, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::V128, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::V128, OpTypes::function32_op, 
    OpTypes::function32_op, 
    OpTypes::EXNREF, 
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::F32, OpTypes::f32imm_op, 
    OpTypes::f32imm_op, 
    OpTypes::F64, OpTypes::f64imm_op, 
    OpTypes::f64imm_op, 
    OpTypes::I32, OpTypes::i32imm_op, 
    OpTypes::i32imm_op, 
    OpTypes::I64, OpTypes::i64imm_op, 
    OpTypes::i64imm_op, 
    OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::f64imm_op, OpTypes::f64imm_op, 
    OpTypes::f64imm_op, OpTypes::f64imm_op, 
    OpTypes::V128, OpTypes::vec_i64imm_op, OpTypes::vec_i64imm_op, 
    OpTypes::vec_i64imm_op, OpTypes::vec_i64imm_op, 
    OpTypes::V128, OpTypes::f32imm_op, OpTypes::f32imm_op, OpTypes::f32imm_op, OpTypes::f32imm_op, 
    OpTypes::f32imm_op, OpTypes::f32imm_op, OpTypes::f32imm_op, OpTypes::f32imm_op, 
    OpTypes::V128, OpTypes::vec_i32imm_op, OpTypes::vec_i32imm_op, OpTypes::vec_i32imm_op, OpTypes::vec_i32imm_op, 
    OpTypes::vec_i32imm_op, OpTypes::vec_i32imm_op, OpTypes::vec_i32imm_op, OpTypes::vec_i32imm_op, 
    OpTypes::V128, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, 
    OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, OpTypes::vec_i16imm_op, 
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::EXNREF, OpTypes::EXNREF, 
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::i32imm_op, 
    OpTypes::i32imm_op, 
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::EXNREF, 
    /**/
    OpTypes::F32, 
    /**/
    OpTypes::F64, 
    /**/
    OpTypes::I32, 
    /**/
    OpTypes::I64, 
    /**/
    OpTypes::V128, 
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    /**/
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, 
    /**/
    OpTypes::I32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::I32, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::I32, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::F64, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::I64, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::F32, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::I32, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::I32, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::I32, OpTypes::V128, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, 
    OpTypes::F32, OpTypes::I32, 
    /**/
    OpTypes::F32, OpTypes::I64, 
    /**/
    OpTypes::F32, OpTypes::I32, 
    /**/
    OpTypes::F32, OpTypes::I64, 
    /**/
    OpTypes::F32, OpTypes::F64, 
    /**/
    OpTypes::F32, OpTypes::I32, 
    /**/
    OpTypes::F64, OpTypes::I32, 
    /**/
    OpTypes::F64, OpTypes::I64, 
    /**/
    OpTypes::F64, OpTypes::I32, 
    /**/
    OpTypes::F64, OpTypes::I64, 
    /**/
    OpTypes::F64, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::I64, 
    /**/
    /**/
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, 
    /**/
    OpTypes::I64, OpTypes::F32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, 
    /**/
    OpTypes::I64, OpTypes::F32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::EXNREF, OpTypes::global_op, 
    OpTypes::global_op, 
    OpTypes::F32, OpTypes::global_op, 
    OpTypes::global_op, 
    OpTypes::F64, OpTypes::global_op, 
    OpTypes::global_op, 
    OpTypes::I32, OpTypes::global_op, 
    OpTypes::global_op, 
    OpTypes::I64, OpTypes::global_op, 
    OpTypes::global_op, 
    OpTypes::V128, OpTypes::global_op, 
    OpTypes::global_op, 
    OpTypes::global_op, OpTypes::EXNREF, 
    OpTypes::global_op, 
    OpTypes::global_op, OpTypes::F32, 
    OpTypes::global_op, 
    OpTypes::global_op, OpTypes::F64, 
    OpTypes::global_op, 
    OpTypes::global_op, OpTypes::I32, 
    OpTypes::global_op, 
    OpTypes::global_op, OpTypes::I64, 
    OpTypes::global_op, 
    OpTypes::global_op, OpTypes::V128, 
    OpTypes::global_op, 
    OpTypes::I32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I64, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I64, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::I64, OpTypes::F32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::I64, OpTypes::F32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::I64, OpTypes::F32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::I64, OpTypes::F32, 
    /**/
    OpTypes::I64, OpTypes::F64, 
    /**/
    OpTypes::Signature, OpTypes::I32, 
    OpTypes::Signature, 
    OpTypes::I32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::F32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::F64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I32, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::I64, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::V128, OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::EXNREF, OpTypes::local_op, 
    OpTypes::local_op, 
    OpTypes::F32, OpTypes::local_op, 
    OpTypes::local_op, 
    OpTypes::F64, OpTypes::local_op, 
    OpTypes::local_op, 
    OpTypes::I32, OpTypes::local_op, 
    OpTypes::local_op, 
    OpTypes::I64, OpTypes::local_op, 
    OpTypes::local_op, 
    OpTypes::V128, OpTypes::local_op, 
    OpTypes::local_op, 
    OpTypes::local_op, OpTypes::EXNREF, 
    OpTypes::local_op, 
    OpTypes::local_op, OpTypes::F32, 
    OpTypes::local_op, 
    OpTypes::local_op, OpTypes::F64, 
    OpTypes::local_op, 
    OpTypes::local_op, OpTypes::I32, 
    OpTypes::local_op, 
    OpTypes::local_op, OpTypes::I64, 
    OpTypes::local_op, 
    OpTypes::local_op, OpTypes::V128, 
    OpTypes::local_op, 
    OpTypes::EXNREF, OpTypes::local_op, OpTypes::EXNREF, 
    OpTypes::local_op, 
    OpTypes::F32, OpTypes::local_op, OpTypes::F32, 
    OpTypes::local_op, 
    OpTypes::F64, OpTypes::local_op, OpTypes::F64, 
    OpTypes::local_op, 
    OpTypes::I32, OpTypes::local_op, OpTypes::I32, 
    OpTypes::local_op, 
    OpTypes::I64, OpTypes::local_op, OpTypes::I64, 
    OpTypes::local_op, 
    OpTypes::V128, OpTypes::local_op, OpTypes::V128, 
    OpTypes::local_op, 
    OpTypes::Signature, 
    OpTypes::Signature, 
    OpTypes::I32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::i32imm_op, OpTypes::i32imm_op, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    OpTypes::i32imm_op, OpTypes::i32imm_op, 
    OpTypes::i32imm_op, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    OpTypes::i32imm_op, 
    OpTypes::I32, OpTypes::i32imm, OpTypes::I32, 
    OpTypes::i32imm, 
    OpTypes::i32imm_op, OpTypes::i32imm_op, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    OpTypes::i32imm_op, OpTypes::i32imm_op, 
    OpTypes::I32, OpTypes::i32imm, 
    OpTypes::i32imm, 
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::I32, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    /**/
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::EXNREF, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::F32, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::F64, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::I32, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::I64, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I32, 
    OpTypes::I32, 
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::I32, 
    OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::F64, 
    OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::I64, 
    OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::F32, 
    OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::I32, 
    OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::I32, 
    OpTypes::vec_i8imm_op, 
    OpTypes::EXNREF, 
    /**/
    /**/
    /**/
    OpTypes::function32_op, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::TypeIndex, OpTypes::i32imm, 
    OpTypes::function32_op, 
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::EXNREF, OpTypes::EXNREF, OpTypes::EXNREF, OpTypes::I32, 
    /**/
    OpTypes::F32, OpTypes::F32, OpTypes::F32, OpTypes::I32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, 
    OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, OpTypes::vec_i8imm_op, 
    OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::F64, 
    /**/
    OpTypes::V128, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::F32, 
    /**/
    OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::V128, OpTypes::I32, 
    /**/
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::F32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::F64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I32, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::I64, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::P2Align, OpTypes::offset32_op, OpTypes::I32, OpTypes::V128, 
    OpTypes::P2Align, OpTypes::offset32_op, 
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::EXNREF, OpTypes::EXNREF, OpTypes::EXNREF, 
    /**/
    OpTypes::F32, OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::event_op, 
    OpTypes::event_op, 
    OpTypes::F32, OpTypes::F32, 
    /**/
    OpTypes::F64, OpTypes::F64, 
    /**/
    OpTypes::Signature, 
    OpTypes::Signature, 
    /**/
    /**/
    OpTypes::I32, OpTypes::I32, OpTypes::I32, 
    /**/
    OpTypes::I64, OpTypes::I64, OpTypes::I64, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
    /**/
    OpTypes::V128, OpTypes::V128, 
  };
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
}
} // end namespace WebAssembly
} // end namespace llvm
#endif // GET_INSTRINFO_OPERAND_TYPE

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO
namespace llvm {

namespace WebAssembly {

enum StackBased {
	StackBased_true
};

// getStackOpcode
LLVM_READONLY
int getStackOpcode(uint16_t Opcode) {
static const uint16_t getStackOpcodeTable[][2] = {
  { WebAssembly::CATCHRET, WebAssembly::CATCHRET_S },
  { WebAssembly::CLEANUPRET, WebAssembly::CLEANUPRET_S },
  { WebAssembly::COMPILER_FENCE, WebAssembly::COMPILER_FENCE_S },
  { WebAssembly::RETHROW_IN_CATCH, WebAssembly::RETHROW_IN_CATCH_S },
  { WebAssembly::ABS_F32, WebAssembly::ABS_F32_S },
  { WebAssembly::ABS_F64, WebAssembly::ABS_F64_S },
  { WebAssembly::ABS_v2f64, WebAssembly::ABS_v2f64_S },
  { WebAssembly::ABS_v4f32, WebAssembly::ABS_v4f32_S },
  { WebAssembly::ADD_F32, WebAssembly::ADD_F32_S },
  { WebAssembly::ADD_F64, WebAssembly::ADD_F64_S },
  { WebAssembly::ADD_I32, WebAssembly::ADD_I32_S },
  { WebAssembly::ADD_I64, WebAssembly::ADD_I64_S },
  { WebAssembly::ADD_SAT_S_v16i8, WebAssembly::ADD_SAT_S_v16i8_S },
  { WebAssembly::ADD_SAT_S_v8i16, WebAssembly::ADD_SAT_S_v8i16_S },
  { WebAssembly::ADD_SAT_U_v16i8, WebAssembly::ADD_SAT_U_v16i8_S },
  { WebAssembly::ADD_SAT_U_v8i16, WebAssembly::ADD_SAT_U_v8i16_S },
  { WebAssembly::ADD_v16i8, WebAssembly::ADD_v16i8_S },
  { WebAssembly::ADD_v2f64, WebAssembly::ADD_v2f64_S },
  { WebAssembly::ADD_v2i64, WebAssembly::ADD_v2i64_S },
  { WebAssembly::ADD_v4f32, WebAssembly::ADD_v4f32_S },
  { WebAssembly::ADD_v4i32, WebAssembly::ADD_v4i32_S },
  { WebAssembly::ADD_v8i16, WebAssembly::ADD_v8i16_S },
  { WebAssembly::ADJCALLSTACKDOWN, WebAssembly::ADJCALLSTACKDOWN_S },
  { WebAssembly::ADJCALLSTACKUP, WebAssembly::ADJCALLSTACKUP_S },
  { WebAssembly::ALLTRUE_v16i8, WebAssembly::ALLTRUE_v16i8_S },
  { WebAssembly::ALLTRUE_v2i64, WebAssembly::ALLTRUE_v2i64_S },
  { WebAssembly::ALLTRUE_v4i32, WebAssembly::ALLTRUE_v4i32_S },
  { WebAssembly::ALLTRUE_v8i16, WebAssembly::ALLTRUE_v8i16_S },
  { WebAssembly::ANDNOT_v16i8, WebAssembly::ANDNOT_v16i8_S },
  { WebAssembly::ANDNOT_v2i64, WebAssembly::ANDNOT_v2i64_S },
  { WebAssembly::ANDNOT_v4i32, WebAssembly::ANDNOT_v4i32_S },
  { WebAssembly::ANDNOT_v8i16, WebAssembly::ANDNOT_v8i16_S },
  { WebAssembly::AND_I32, WebAssembly::AND_I32_S },
  { WebAssembly::AND_I64, WebAssembly::AND_I64_S },
  { WebAssembly::AND_v16i8, WebAssembly::AND_v16i8_S },
  { WebAssembly::AND_v2i64, WebAssembly::AND_v2i64_S },
  { WebAssembly::AND_v4i32, WebAssembly::AND_v4i32_S },
  { WebAssembly::AND_v8i16, WebAssembly::AND_v8i16_S },
  { WebAssembly::ANYTRUE_v16i8, WebAssembly::ANYTRUE_v16i8_S },
  { WebAssembly::ANYTRUE_v2i64, WebAssembly::ANYTRUE_v2i64_S },
  { WebAssembly::ANYTRUE_v4i32, WebAssembly::ANYTRUE_v4i32_S },
  { WebAssembly::ANYTRUE_v8i16, WebAssembly::ANYTRUE_v8i16_S },
  { WebAssembly::ARGUMENT_exnref, WebAssembly::ARGUMENT_exnref_S },
  { WebAssembly::ARGUMENT_f32, WebAssembly::ARGUMENT_f32_S },
  { WebAssembly::ARGUMENT_f64, WebAssembly::ARGUMENT_f64_S },
  { WebAssembly::ARGUMENT_i32, WebAssembly::ARGUMENT_i32_S },
  { WebAssembly::ARGUMENT_i64, WebAssembly::ARGUMENT_i64_S },
  { WebAssembly::ARGUMENT_v16i8, WebAssembly::ARGUMENT_v16i8_S },
  { WebAssembly::ARGUMENT_v2f64, WebAssembly::ARGUMENT_v2f64_S },
  { WebAssembly::ARGUMENT_v2i64, WebAssembly::ARGUMENT_v2i64_S },
  { WebAssembly::ARGUMENT_v4f32, WebAssembly::ARGUMENT_v4f32_S },
  { WebAssembly::ARGUMENT_v4i32, WebAssembly::ARGUMENT_v4i32_S },
  { WebAssembly::ARGUMENT_v8i16, WebAssembly::ARGUMENT_v8i16_S },
  { WebAssembly::ATOMIC_FENCE, WebAssembly::ATOMIC_FENCE_S },
  { WebAssembly::ATOMIC_LOAD16_U_I32, WebAssembly::ATOMIC_LOAD16_U_I32_S },
  { WebAssembly::ATOMIC_LOAD16_U_I64, WebAssembly::ATOMIC_LOAD16_U_I64_S },
  { WebAssembly::ATOMIC_LOAD32_U_I64, WebAssembly::ATOMIC_LOAD32_U_I64_S },
  { WebAssembly::ATOMIC_LOAD8_U_I32, WebAssembly::ATOMIC_LOAD8_U_I32_S },
  { WebAssembly::ATOMIC_LOAD8_U_I64, WebAssembly::ATOMIC_LOAD8_U_I64_S },
  { WebAssembly::ATOMIC_LOAD_I32, WebAssembly::ATOMIC_LOAD_I32_S },
  { WebAssembly::ATOMIC_LOAD_I64, WebAssembly::ATOMIC_LOAD_I64_S },
  { WebAssembly::ATOMIC_NOTIFY, WebAssembly::ATOMIC_NOTIFY_S },
  { WebAssembly::ATOMIC_RMW16_U_ADD_I32, WebAssembly::ATOMIC_RMW16_U_ADD_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_ADD_I64, WebAssembly::ATOMIC_RMW16_U_ADD_I64_S },
  { WebAssembly::ATOMIC_RMW16_U_AND_I32, WebAssembly::ATOMIC_RMW16_U_AND_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_AND_I64, WebAssembly::ATOMIC_RMW16_U_AND_I64_S },
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64, WebAssembly::ATOMIC_RMW16_U_CMPXCHG_I64_S },
  { WebAssembly::ATOMIC_RMW16_U_OR_I32, WebAssembly::ATOMIC_RMW16_U_OR_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_OR_I64, WebAssembly::ATOMIC_RMW16_U_OR_I64_S },
  { WebAssembly::ATOMIC_RMW16_U_SUB_I32, WebAssembly::ATOMIC_RMW16_U_SUB_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_SUB_I64, WebAssembly::ATOMIC_RMW16_U_SUB_I64_S },
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I32, WebAssembly::ATOMIC_RMW16_U_XCHG_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_XCHG_I64, WebAssembly::ATOMIC_RMW16_U_XCHG_I64_S },
  { WebAssembly::ATOMIC_RMW16_U_XOR_I32, WebAssembly::ATOMIC_RMW16_U_XOR_I32_S },
  { WebAssembly::ATOMIC_RMW16_U_XOR_I64, WebAssembly::ATOMIC_RMW16_U_XOR_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_ADD_I64, WebAssembly::ATOMIC_RMW32_U_ADD_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_AND_I64, WebAssembly::ATOMIC_RMW32_U_AND_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64, WebAssembly::ATOMIC_RMW32_U_CMPXCHG_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_OR_I64, WebAssembly::ATOMIC_RMW32_U_OR_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_SUB_I64, WebAssembly::ATOMIC_RMW32_U_SUB_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_XCHG_I64, WebAssembly::ATOMIC_RMW32_U_XCHG_I64_S },
  { WebAssembly::ATOMIC_RMW32_U_XOR_I64, WebAssembly::ATOMIC_RMW32_U_XOR_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_ADD_I32, WebAssembly::ATOMIC_RMW8_U_ADD_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_ADD_I64, WebAssembly::ATOMIC_RMW8_U_ADD_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_AND_I32, WebAssembly::ATOMIC_RMW8_U_AND_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_AND_I64, WebAssembly::ATOMIC_RMW8_U_AND_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64, WebAssembly::ATOMIC_RMW8_U_CMPXCHG_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_OR_I32, WebAssembly::ATOMIC_RMW8_U_OR_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_OR_I64, WebAssembly::ATOMIC_RMW8_U_OR_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_SUB_I32, WebAssembly::ATOMIC_RMW8_U_SUB_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_SUB_I64, WebAssembly::ATOMIC_RMW8_U_SUB_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I32, WebAssembly::ATOMIC_RMW8_U_XCHG_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_XCHG_I64, WebAssembly::ATOMIC_RMW8_U_XCHG_I64_S },
  { WebAssembly::ATOMIC_RMW8_U_XOR_I32, WebAssembly::ATOMIC_RMW8_U_XOR_I32_S },
  { WebAssembly::ATOMIC_RMW8_U_XOR_I64, WebAssembly::ATOMIC_RMW8_U_XOR_I64_S },
  { WebAssembly::ATOMIC_RMW_ADD_I32, WebAssembly::ATOMIC_RMW_ADD_I32_S },
  { WebAssembly::ATOMIC_RMW_ADD_I64, WebAssembly::ATOMIC_RMW_ADD_I64_S },
  { WebAssembly::ATOMIC_RMW_AND_I32, WebAssembly::ATOMIC_RMW_AND_I32_S },
  { WebAssembly::ATOMIC_RMW_AND_I64, WebAssembly::ATOMIC_RMW_AND_I64_S },
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I32, WebAssembly::ATOMIC_RMW_CMPXCHG_I32_S },
  { WebAssembly::ATOMIC_RMW_CMPXCHG_I64, WebAssembly::ATOMIC_RMW_CMPXCHG_I64_S },
  { WebAssembly::ATOMIC_RMW_OR_I32, WebAssembly::ATOMIC_RMW_OR_I32_S },
  { WebAssembly::ATOMIC_RMW_OR_I64, WebAssembly::ATOMIC_RMW_OR_I64_S },
  { WebAssembly::ATOMIC_RMW_SUB_I32, WebAssembly::ATOMIC_RMW_SUB_I32_S },
  { WebAssembly::ATOMIC_RMW_SUB_I64, WebAssembly::ATOMIC_RMW_SUB_I64_S },
  { WebAssembly::ATOMIC_RMW_XCHG_I32, WebAssembly::ATOMIC_RMW_XCHG_I32_S },
  { WebAssembly::ATOMIC_RMW_XCHG_I64, WebAssembly::ATOMIC_RMW_XCHG_I64_S },
  { WebAssembly::ATOMIC_RMW_XOR_I32, WebAssembly::ATOMIC_RMW_XOR_I32_S },
  { WebAssembly::ATOMIC_RMW_XOR_I64, WebAssembly::ATOMIC_RMW_XOR_I64_S },
  { WebAssembly::ATOMIC_STORE16_I32, WebAssembly::ATOMIC_STORE16_I32_S },
  { WebAssembly::ATOMIC_STORE16_I64, WebAssembly::ATOMIC_STORE16_I64_S },
  { WebAssembly::ATOMIC_STORE32_I64, WebAssembly::ATOMIC_STORE32_I64_S },
  { WebAssembly::ATOMIC_STORE8_I32, WebAssembly::ATOMIC_STORE8_I32_S },
  { WebAssembly::ATOMIC_STORE8_I64, WebAssembly::ATOMIC_STORE8_I64_S },
  { WebAssembly::ATOMIC_STORE_I32, WebAssembly::ATOMIC_STORE_I32_S },
  { WebAssembly::ATOMIC_STORE_I64, WebAssembly::ATOMIC_STORE_I64_S },
  { WebAssembly::ATOMIC_WAIT_I32, WebAssembly::ATOMIC_WAIT_I32_S },
  { WebAssembly::ATOMIC_WAIT_I64, WebAssembly::ATOMIC_WAIT_I64_S },
  { WebAssembly::BITSELECT_v16i8, WebAssembly::BITSELECT_v16i8_S },
  { WebAssembly::BITSELECT_v2f64, WebAssembly::BITSELECT_v2f64_S },
  { WebAssembly::BITSELECT_v2i64, WebAssembly::BITSELECT_v2i64_S },
  { WebAssembly::BITSELECT_v4f32, WebAssembly::BITSELECT_v4f32_S },
  { WebAssembly::BITSELECT_v4i32, WebAssembly::BITSELECT_v4i32_S },
  { WebAssembly::BITSELECT_v8i16, WebAssembly::BITSELECT_v8i16_S },
  { WebAssembly::BLOCK, WebAssembly::BLOCK_S },
  { WebAssembly::BR, WebAssembly::BR_S },
  { WebAssembly::BR_IF, WebAssembly::BR_IF_S },
  { WebAssembly::BR_ON_EXN, WebAssembly::BR_ON_EXN_S },
  { WebAssembly::BR_TABLE_I32, WebAssembly::BR_TABLE_I32_S },
  { WebAssembly::BR_TABLE_I64, WebAssembly::BR_TABLE_I64_S },
  { WebAssembly::BR_UNLESS, WebAssembly::BR_UNLESS_S },
  { WebAssembly::CALL_INDIRECT_VOID, WebAssembly::CALL_INDIRECT_VOID_S },
  { WebAssembly::CALL_INDIRECT_exnref, WebAssembly::CALL_INDIRECT_exnref_S },
  { WebAssembly::CALL_INDIRECT_f32, WebAssembly::CALL_INDIRECT_f32_S },
  { WebAssembly::CALL_INDIRECT_f64, WebAssembly::CALL_INDIRECT_f64_S },
  { WebAssembly::CALL_INDIRECT_i32, WebAssembly::CALL_INDIRECT_i32_S },
  { WebAssembly::CALL_INDIRECT_i64, WebAssembly::CALL_INDIRECT_i64_S },
  { WebAssembly::CALL_INDIRECT_v16i8, WebAssembly::CALL_INDIRECT_v16i8_S },
  { WebAssembly::CALL_INDIRECT_v2f64, WebAssembly::CALL_INDIRECT_v2f64_S },
  { WebAssembly::CALL_INDIRECT_v2i64, WebAssembly::CALL_INDIRECT_v2i64_S },
  { WebAssembly::CALL_INDIRECT_v4f32, WebAssembly::CALL_INDIRECT_v4f32_S },
  { WebAssembly::CALL_INDIRECT_v4i32, WebAssembly::CALL_INDIRECT_v4i32_S },
  { WebAssembly::CALL_INDIRECT_v8i16, WebAssembly::CALL_INDIRECT_v8i16_S },
  { WebAssembly::CALL_VOID, WebAssembly::CALL_VOID_S },
  { WebAssembly::CALL_exnref, WebAssembly::CALL_exnref_S },
  { WebAssembly::CALL_f32, WebAssembly::CALL_f32_S },
  { WebAssembly::CALL_f64, WebAssembly::CALL_f64_S },
  { WebAssembly::CALL_i32, WebAssembly::CALL_i32_S },
  { WebAssembly::CALL_i64, WebAssembly::CALL_i64_S },
  { WebAssembly::CALL_v16i8, WebAssembly::CALL_v16i8_S },
  { WebAssembly::CALL_v2f64, WebAssembly::CALL_v2f64_S },
  { WebAssembly::CALL_v2i64, WebAssembly::CALL_v2i64_S },
  { WebAssembly::CALL_v4f32, WebAssembly::CALL_v4f32_S },
  { WebAssembly::CALL_v4i32, WebAssembly::CALL_v4i32_S },
  { WebAssembly::CALL_v8i16, WebAssembly::CALL_v8i16_S },
  { WebAssembly::CATCH, WebAssembly::CATCH_S },
  { WebAssembly::CEIL_F32, WebAssembly::CEIL_F32_S },
  { WebAssembly::CEIL_F64, WebAssembly::CEIL_F64_S },
  { WebAssembly::CLZ_I32, WebAssembly::CLZ_I32_S },
  { WebAssembly::CLZ_I64, WebAssembly::CLZ_I64_S },
  { WebAssembly::CONST_F32, WebAssembly::CONST_F32_S },
  { WebAssembly::CONST_F64, WebAssembly::CONST_F64_S },
  { WebAssembly::CONST_I32, WebAssembly::CONST_I32_S },
  { WebAssembly::CONST_I64, WebAssembly::CONST_I64_S },
  { WebAssembly::CONST_V128_v16i8, WebAssembly::CONST_V128_v16i8_S },
  { WebAssembly::CONST_V128_v2f64, WebAssembly::CONST_V128_v2f64_S },
  { WebAssembly::CONST_V128_v2i64, WebAssembly::CONST_V128_v2i64_S },
  { WebAssembly::CONST_V128_v4f32, WebAssembly::CONST_V128_v4f32_S },
  { WebAssembly::CONST_V128_v4i32, WebAssembly::CONST_V128_v4i32_S },
  { WebAssembly::CONST_V128_v8i16, WebAssembly::CONST_V128_v8i16_S },
  { WebAssembly::COPYSIGN_F32, WebAssembly::COPYSIGN_F32_S },
  { WebAssembly::COPYSIGN_F64, WebAssembly::COPYSIGN_F64_S },
  { WebAssembly::COPY_EXNREF, WebAssembly::COPY_EXNREF_S },
  { WebAssembly::COPY_F32, WebAssembly::COPY_F32_S },
  { WebAssembly::COPY_F64, WebAssembly::COPY_F64_S },
  { WebAssembly::COPY_I32, WebAssembly::COPY_I32_S },
  { WebAssembly::COPY_I64, WebAssembly::COPY_I64_S },
  { WebAssembly::COPY_V128, WebAssembly::COPY_V128_S },
  { WebAssembly::CTZ_I32, WebAssembly::CTZ_I32_S },
  { WebAssembly::CTZ_I64, WebAssembly::CTZ_I64_S },
  { WebAssembly::DATA_DROP, WebAssembly::DATA_DROP_S },
  { WebAssembly::DIV_F32, WebAssembly::DIV_F32_S },
  { WebAssembly::DIV_F64, WebAssembly::DIV_F64_S },
  { WebAssembly::DIV_S_I32, WebAssembly::DIV_S_I32_S },
  { WebAssembly::DIV_S_I64, WebAssembly::DIV_S_I64_S },
  { WebAssembly::DIV_U_I32, WebAssembly::DIV_U_I32_S },
  { WebAssembly::DIV_U_I64, WebAssembly::DIV_U_I64_S },
  { WebAssembly::DIV_v2f64, WebAssembly::DIV_v2f64_S },
  { WebAssembly::DIV_v4f32, WebAssembly::DIV_v4f32_S },
  { WebAssembly::DROP_EXNREF, WebAssembly::DROP_EXNREF_S },
  { WebAssembly::DROP_F32, WebAssembly::DROP_F32_S },
  { WebAssembly::DROP_F64, WebAssembly::DROP_F64_S },
  { WebAssembly::DROP_I32, WebAssembly::DROP_I32_S },
  { WebAssembly::DROP_I64, WebAssembly::DROP_I64_S },
  { WebAssembly::DROP_V128, WebAssembly::DROP_V128_S },
  { WebAssembly::ELSE, WebAssembly::ELSE_S },
  { WebAssembly::END, WebAssembly::END_S },
  { WebAssembly::END_BLOCK, WebAssembly::END_BLOCK_S },
  { WebAssembly::END_FUNCTION, WebAssembly::END_FUNCTION_S },
  { WebAssembly::END_IF, WebAssembly::END_IF_S },
  { WebAssembly::END_LOOP, WebAssembly::END_LOOP_S },
  { WebAssembly::END_TRY, WebAssembly::END_TRY_S },
  { WebAssembly::EQZ_I32, WebAssembly::EQZ_I32_S },
  { WebAssembly::EQZ_I64, WebAssembly::EQZ_I64_S },
  { WebAssembly::EQ_F32, WebAssembly::EQ_F32_S },
  { WebAssembly::EQ_F64, WebAssembly::EQ_F64_S },
  { WebAssembly::EQ_I32, WebAssembly::EQ_I32_S },
  { WebAssembly::EQ_I64, WebAssembly::EQ_I64_S },
  { WebAssembly::EQ_v16i8, WebAssembly::EQ_v16i8_S },
  { WebAssembly::EQ_v2f64, WebAssembly::EQ_v2f64_S },
  { WebAssembly::EQ_v4f32, WebAssembly::EQ_v4f32_S },
  { WebAssembly::EQ_v4i32, WebAssembly::EQ_v4i32_S },
  { WebAssembly::EQ_v8i16, WebAssembly::EQ_v8i16_S },
  { WebAssembly::EXTRACT_EXCEPTION_I32, WebAssembly::EXTRACT_EXCEPTION_I32_S },
  { WebAssembly::EXTRACT_LANE_v16i8_s, WebAssembly::EXTRACT_LANE_v16i8_s_S },
  { WebAssembly::EXTRACT_LANE_v16i8_u, WebAssembly::EXTRACT_LANE_v16i8_u_S },
  { WebAssembly::EXTRACT_LANE_v2f64, WebAssembly::EXTRACT_LANE_v2f64_S },
  { WebAssembly::EXTRACT_LANE_v2i64, WebAssembly::EXTRACT_LANE_v2i64_S },
  { WebAssembly::EXTRACT_LANE_v4f32, WebAssembly::EXTRACT_LANE_v4f32_S },
  { WebAssembly::EXTRACT_LANE_v4i32, WebAssembly::EXTRACT_LANE_v4i32_S },
  { WebAssembly::EXTRACT_LANE_v8i16_s, WebAssembly::EXTRACT_LANE_v8i16_s_S },
  { WebAssembly::EXTRACT_LANE_v8i16_u, WebAssembly::EXTRACT_LANE_v8i16_u_S },
  { WebAssembly::F32_CONVERT_S_I32, WebAssembly::F32_CONVERT_S_I32_S },
  { WebAssembly::F32_CONVERT_S_I64, WebAssembly::F32_CONVERT_S_I64_S },
  { WebAssembly::F32_CONVERT_U_I32, WebAssembly::F32_CONVERT_U_I32_S },
  { WebAssembly::F32_CONVERT_U_I64, WebAssembly::F32_CONVERT_U_I64_S },
  { WebAssembly::F32_DEMOTE_F64, WebAssembly::F32_DEMOTE_F64_S },
  { WebAssembly::F32_REINTERPRET_I32, WebAssembly::F32_REINTERPRET_I32_S },
  { WebAssembly::F64_CONVERT_S_I32, WebAssembly::F64_CONVERT_S_I32_S },
  { WebAssembly::F64_CONVERT_S_I64, WebAssembly::F64_CONVERT_S_I64_S },
  { WebAssembly::F64_CONVERT_U_I32, WebAssembly::F64_CONVERT_U_I32_S },
  { WebAssembly::F64_CONVERT_U_I64, WebAssembly::F64_CONVERT_U_I64_S },
  { WebAssembly::F64_PROMOTE_F32, WebAssembly::F64_PROMOTE_F32_S },
  { WebAssembly::F64_REINTERPRET_I64, WebAssembly::F64_REINTERPRET_I64_S },
  { WebAssembly::FALLTHROUGH_RETURN, WebAssembly::FALLTHROUGH_RETURN_S },
  { WebAssembly::FLOOR_F32, WebAssembly::FLOOR_F32_S },
  { WebAssembly::FLOOR_F64, WebAssembly::FLOOR_F64_S },
  { WebAssembly::FP_TO_SINT_I32_F32, WebAssembly::FP_TO_SINT_I32_F32_S },
  { WebAssembly::FP_TO_SINT_I32_F64, WebAssembly::FP_TO_SINT_I32_F64_S },
  { WebAssembly::FP_TO_SINT_I64_F32, WebAssembly::FP_TO_SINT_I64_F32_S },
  { WebAssembly::FP_TO_SINT_I64_F64, WebAssembly::FP_TO_SINT_I64_F64_S },
  { WebAssembly::FP_TO_UINT_I32_F32, WebAssembly::FP_TO_UINT_I32_F32_S },
  { WebAssembly::FP_TO_UINT_I32_F64, WebAssembly::FP_TO_UINT_I32_F64_S },
  { WebAssembly::FP_TO_UINT_I64_F32, WebAssembly::FP_TO_UINT_I64_F32_S },
  { WebAssembly::FP_TO_UINT_I64_F64, WebAssembly::FP_TO_UINT_I64_F64_S },
  { WebAssembly::GE_F32, WebAssembly::GE_F32_S },
  { WebAssembly::GE_F64, WebAssembly::GE_F64_S },
  { WebAssembly::GE_S_I32, WebAssembly::GE_S_I32_S },
  { WebAssembly::GE_S_I64, WebAssembly::GE_S_I64_S },
  { WebAssembly::GE_S_v16i8, WebAssembly::GE_S_v16i8_S },
  { WebAssembly::GE_S_v4i32, WebAssembly::GE_S_v4i32_S },
  { WebAssembly::GE_S_v8i16, WebAssembly::GE_S_v8i16_S },
  { WebAssembly::GE_U_I32, WebAssembly::GE_U_I32_S },
  { WebAssembly::GE_U_I64, WebAssembly::GE_U_I64_S },
  { WebAssembly::GE_U_v16i8, WebAssembly::GE_U_v16i8_S },
  { WebAssembly::GE_U_v4i32, WebAssembly::GE_U_v4i32_S },
  { WebAssembly::GE_U_v8i16, WebAssembly::GE_U_v8i16_S },
  { WebAssembly::GE_v2f64, WebAssembly::GE_v2f64_S },
  { WebAssembly::GE_v4f32, WebAssembly::GE_v4f32_S },
  { WebAssembly::GLOBAL_GET_EXNREF, WebAssembly::GLOBAL_GET_EXNREF_S },
  { WebAssembly::GLOBAL_GET_F32, WebAssembly::GLOBAL_GET_F32_S },
  { WebAssembly::GLOBAL_GET_F64, WebAssembly::GLOBAL_GET_F64_S },
  { WebAssembly::GLOBAL_GET_I32, WebAssembly::GLOBAL_GET_I32_S },
  { WebAssembly::GLOBAL_GET_I64, WebAssembly::GLOBAL_GET_I64_S },
  { WebAssembly::GLOBAL_GET_V128, WebAssembly::GLOBAL_GET_V128_S },
  { WebAssembly::GLOBAL_SET_EXNREF, WebAssembly::GLOBAL_SET_EXNREF_S },
  { WebAssembly::GLOBAL_SET_F32, WebAssembly::GLOBAL_SET_F32_S },
  { WebAssembly::GLOBAL_SET_F64, WebAssembly::GLOBAL_SET_F64_S },
  { WebAssembly::GLOBAL_SET_I32, WebAssembly::GLOBAL_SET_I32_S },
  { WebAssembly::GLOBAL_SET_I64, WebAssembly::GLOBAL_SET_I64_S },
  { WebAssembly::GLOBAL_SET_V128, WebAssembly::GLOBAL_SET_V128_S },
  { WebAssembly::GT_F32, WebAssembly::GT_F32_S },
  { WebAssembly::GT_F64, WebAssembly::GT_F64_S },
  { WebAssembly::GT_S_I32, WebAssembly::GT_S_I32_S },
  { WebAssembly::GT_S_I64, WebAssembly::GT_S_I64_S },
  { WebAssembly::GT_S_v16i8, WebAssembly::GT_S_v16i8_S },
  { WebAssembly::GT_S_v4i32, WebAssembly::GT_S_v4i32_S },
  { WebAssembly::GT_S_v8i16, WebAssembly::GT_S_v8i16_S },
  { WebAssembly::GT_U_I32, WebAssembly::GT_U_I32_S },
  { WebAssembly::GT_U_I64, WebAssembly::GT_U_I64_S },
  { WebAssembly::GT_U_v16i8, WebAssembly::GT_U_v16i8_S },
  { WebAssembly::GT_U_v4i32, WebAssembly::GT_U_v4i32_S },
  { WebAssembly::GT_U_v8i16, WebAssembly::GT_U_v8i16_S },
  { WebAssembly::GT_v2f64, WebAssembly::GT_v2f64_S },
  { WebAssembly::GT_v4f32, WebAssembly::GT_v4f32_S },
  { WebAssembly::I32_EXTEND16_S_I32, WebAssembly::I32_EXTEND16_S_I32_S },
  { WebAssembly::I32_EXTEND8_S_I32, WebAssembly::I32_EXTEND8_S_I32_S },
  { WebAssembly::I32_REINTERPRET_F32, WebAssembly::I32_REINTERPRET_F32_S },
  { WebAssembly::I32_TRUNC_S_F32, WebAssembly::I32_TRUNC_S_F32_S },
  { WebAssembly::I32_TRUNC_S_F64, WebAssembly::I32_TRUNC_S_F64_S },
  { WebAssembly::I32_TRUNC_S_SAT_F32, WebAssembly::I32_TRUNC_S_SAT_F32_S },
  { WebAssembly::I32_TRUNC_S_SAT_F64, WebAssembly::I32_TRUNC_S_SAT_F64_S },
  { WebAssembly::I32_TRUNC_U_F32, WebAssembly::I32_TRUNC_U_F32_S },
  { WebAssembly::I32_TRUNC_U_F64, WebAssembly::I32_TRUNC_U_F64_S },
  { WebAssembly::I32_TRUNC_U_SAT_F32, WebAssembly::I32_TRUNC_U_SAT_F32_S },
  { WebAssembly::I32_TRUNC_U_SAT_F64, WebAssembly::I32_TRUNC_U_SAT_F64_S },
  { WebAssembly::I32_WRAP_I64, WebAssembly::I32_WRAP_I64_S },
  { WebAssembly::I64_EXTEND16_S_I64, WebAssembly::I64_EXTEND16_S_I64_S },
  { WebAssembly::I64_EXTEND32_S_I64, WebAssembly::I64_EXTEND32_S_I64_S },
  { WebAssembly::I64_EXTEND8_S_I64, WebAssembly::I64_EXTEND8_S_I64_S },
  { WebAssembly::I64_EXTEND_S_I32, WebAssembly::I64_EXTEND_S_I32_S },
  { WebAssembly::I64_EXTEND_U_I32, WebAssembly::I64_EXTEND_U_I32_S },
  { WebAssembly::I64_REINTERPRET_F64, WebAssembly::I64_REINTERPRET_F64_S },
  { WebAssembly::I64_TRUNC_S_F32, WebAssembly::I64_TRUNC_S_F32_S },
  { WebAssembly::I64_TRUNC_S_F64, WebAssembly::I64_TRUNC_S_F64_S },
  { WebAssembly::I64_TRUNC_S_SAT_F32, WebAssembly::I64_TRUNC_S_SAT_F32_S },
  { WebAssembly::I64_TRUNC_S_SAT_F64, WebAssembly::I64_TRUNC_S_SAT_F64_S },
  { WebAssembly::I64_TRUNC_U_F32, WebAssembly::I64_TRUNC_U_F32_S },
  { WebAssembly::I64_TRUNC_U_F64, WebAssembly::I64_TRUNC_U_F64_S },
  { WebAssembly::I64_TRUNC_U_SAT_F32, WebAssembly::I64_TRUNC_U_SAT_F32_S },
  { WebAssembly::I64_TRUNC_U_SAT_F64, WebAssembly::I64_TRUNC_U_SAT_F64_S },
  { WebAssembly::IF, WebAssembly::IF_S },
  { WebAssembly::LE_F32, WebAssembly::LE_F32_S },
  { WebAssembly::LE_F64, WebAssembly::LE_F64_S },
  { WebAssembly::LE_S_I32, WebAssembly::LE_S_I32_S },
  { WebAssembly::LE_S_I64, WebAssembly::LE_S_I64_S },
  { WebAssembly::LE_S_v16i8, WebAssembly::LE_S_v16i8_S },
  { WebAssembly::LE_S_v4i32, WebAssembly::LE_S_v4i32_S },
  { WebAssembly::LE_S_v8i16, WebAssembly::LE_S_v8i16_S },
  { WebAssembly::LE_U_I32, WebAssembly::LE_U_I32_S },
  { WebAssembly::LE_U_I64, WebAssembly::LE_U_I64_S },
  { WebAssembly::LE_U_v16i8, WebAssembly::LE_U_v16i8_S },
  { WebAssembly::LE_U_v4i32, WebAssembly::LE_U_v4i32_S },
  { WebAssembly::LE_U_v8i16, WebAssembly::LE_U_v8i16_S },
  { WebAssembly::LE_v2f64, WebAssembly::LE_v2f64_S },
  { WebAssembly::LE_v4f32, WebAssembly::LE_v4f32_S },
  { WebAssembly::LOAD16_S_I32, WebAssembly::LOAD16_S_I32_S },
  { WebAssembly::LOAD16_S_I64, WebAssembly::LOAD16_S_I64_S },
  { WebAssembly::LOAD16_U_I32, WebAssembly::LOAD16_U_I32_S },
  { WebAssembly::LOAD16_U_I64, WebAssembly::LOAD16_U_I64_S },
  { WebAssembly::LOAD32_S_I64, WebAssembly::LOAD32_S_I64_S },
  { WebAssembly::LOAD32_U_I64, WebAssembly::LOAD32_U_I64_S },
  { WebAssembly::LOAD8_S_I32, WebAssembly::LOAD8_S_I32_S },
  { WebAssembly::LOAD8_S_I64, WebAssembly::LOAD8_S_I64_S },
  { WebAssembly::LOAD8_U_I32, WebAssembly::LOAD8_U_I32_S },
  { WebAssembly::LOAD8_U_I64, WebAssembly::LOAD8_U_I64_S },
  { WebAssembly::LOAD_EXTEND_S_v2i64, WebAssembly::LOAD_EXTEND_S_v2i64_S },
  { WebAssembly::LOAD_EXTEND_S_v4i32, WebAssembly::LOAD_EXTEND_S_v4i32_S },
  { WebAssembly::LOAD_EXTEND_S_v8i16, WebAssembly::LOAD_EXTEND_S_v8i16_S },
  { WebAssembly::LOAD_EXTEND_U_v2i64, WebAssembly::LOAD_EXTEND_U_v2i64_S },
  { WebAssembly::LOAD_EXTEND_U_v4i32, WebAssembly::LOAD_EXTEND_U_v4i32_S },
  { WebAssembly::LOAD_EXTEND_U_v8i16, WebAssembly::LOAD_EXTEND_U_v8i16_S },
  { WebAssembly::LOAD_F32, WebAssembly::LOAD_F32_S },
  { WebAssembly::LOAD_F64, WebAssembly::LOAD_F64_S },
  { WebAssembly::LOAD_I32, WebAssembly::LOAD_I32_S },
  { WebAssembly::LOAD_I64, WebAssembly::LOAD_I64_S },
  { WebAssembly::LOAD_SPLAT_v16x8, WebAssembly::LOAD_SPLAT_v16x8_S },
  { WebAssembly::LOAD_SPLAT_v32x4, WebAssembly::LOAD_SPLAT_v32x4_S },
  { WebAssembly::LOAD_SPLAT_v64x2, WebAssembly::LOAD_SPLAT_v64x2_S },
  { WebAssembly::LOAD_SPLAT_v8x16, WebAssembly::LOAD_SPLAT_v8x16_S },
  { WebAssembly::LOAD_V128, WebAssembly::LOAD_V128_S },
  { WebAssembly::LOCAL_GET_EXNREF, WebAssembly::LOCAL_GET_EXNREF_S },
  { WebAssembly::LOCAL_GET_F32, WebAssembly::LOCAL_GET_F32_S },
  { WebAssembly::LOCAL_GET_F64, WebAssembly::LOCAL_GET_F64_S },
  { WebAssembly::LOCAL_GET_I32, WebAssembly::LOCAL_GET_I32_S },
  { WebAssembly::LOCAL_GET_I64, WebAssembly::LOCAL_GET_I64_S },
  { WebAssembly::LOCAL_GET_V128, WebAssembly::LOCAL_GET_V128_S },
  { WebAssembly::LOCAL_SET_EXNREF, WebAssembly::LOCAL_SET_EXNREF_S },
  { WebAssembly::LOCAL_SET_F32, WebAssembly::LOCAL_SET_F32_S },
  { WebAssembly::LOCAL_SET_F64, WebAssembly::LOCAL_SET_F64_S },
  { WebAssembly::LOCAL_SET_I32, WebAssembly::LOCAL_SET_I32_S },
  { WebAssembly::LOCAL_SET_I64, WebAssembly::LOCAL_SET_I64_S },
  { WebAssembly::LOCAL_SET_V128, WebAssembly::LOCAL_SET_V128_S },
  { WebAssembly::LOCAL_TEE_EXNREF, WebAssembly::LOCAL_TEE_EXNREF_S },
  { WebAssembly::LOCAL_TEE_F32, WebAssembly::LOCAL_TEE_F32_S },
  { WebAssembly::LOCAL_TEE_F64, WebAssembly::LOCAL_TEE_F64_S },
  { WebAssembly::LOCAL_TEE_I32, WebAssembly::LOCAL_TEE_I32_S },
  { WebAssembly::LOCAL_TEE_I64, WebAssembly::LOCAL_TEE_I64_S },
  { WebAssembly::LOCAL_TEE_V128, WebAssembly::LOCAL_TEE_V128_S },
  { WebAssembly::LOOP, WebAssembly::LOOP_S },
  { WebAssembly::LT_F32, WebAssembly::LT_F32_S },
  { WebAssembly::LT_F64, WebAssembly::LT_F64_S },
  { WebAssembly::LT_S_I32, WebAssembly::LT_S_I32_S },
  { WebAssembly::LT_S_I64, WebAssembly::LT_S_I64_S },
  { WebAssembly::LT_S_v16i8, WebAssembly::LT_S_v16i8_S },
  { WebAssembly::LT_S_v4i32, WebAssembly::LT_S_v4i32_S },
  { WebAssembly::LT_S_v8i16, WebAssembly::LT_S_v8i16_S },
  { WebAssembly::LT_U_I32, WebAssembly::LT_U_I32_S },
  { WebAssembly::LT_U_I64, WebAssembly::LT_U_I64_S },
  { WebAssembly::LT_U_v16i8, WebAssembly::LT_U_v16i8_S },
  { WebAssembly::LT_U_v4i32, WebAssembly::LT_U_v4i32_S },
  { WebAssembly::LT_U_v8i16, WebAssembly::LT_U_v8i16_S },
  { WebAssembly::LT_v2f64, WebAssembly::LT_v2f64_S },
  { WebAssembly::LT_v4f32, WebAssembly::LT_v4f32_S },
  { WebAssembly::MAX_F32, WebAssembly::MAX_F32_S },
  { WebAssembly::MAX_F64, WebAssembly::MAX_F64_S },
  { WebAssembly::MAX_v2f64, WebAssembly::MAX_v2f64_S },
  { WebAssembly::MAX_v4f32, WebAssembly::MAX_v4f32_S },
  { WebAssembly::MEMORY_COPY, WebAssembly::MEMORY_COPY_S },
  { WebAssembly::MEMORY_FILL, WebAssembly::MEMORY_FILL_S },
  { WebAssembly::MEMORY_GROW_I32, WebAssembly::MEMORY_GROW_I32_S },
  { WebAssembly::MEMORY_INIT, WebAssembly::MEMORY_INIT_S },
  { WebAssembly::MEMORY_SIZE_I32, WebAssembly::MEMORY_SIZE_I32_S },
  { WebAssembly::MIN_F32, WebAssembly::MIN_F32_S },
  { WebAssembly::MIN_F64, WebAssembly::MIN_F64_S },
  { WebAssembly::MIN_v2f64, WebAssembly::MIN_v2f64_S },
  { WebAssembly::MIN_v4f32, WebAssembly::MIN_v4f32_S },
  { WebAssembly::MUL_F32, WebAssembly::MUL_F32_S },
  { WebAssembly::MUL_F64, WebAssembly::MUL_F64_S },
  { WebAssembly::MUL_I32, WebAssembly::MUL_I32_S },
  { WebAssembly::MUL_I64, WebAssembly::MUL_I64_S },
  { WebAssembly::MUL_v16i8, WebAssembly::MUL_v16i8_S },
  { WebAssembly::MUL_v2f64, WebAssembly::MUL_v2f64_S },
  { WebAssembly::MUL_v4f32, WebAssembly::MUL_v4f32_S },
  { WebAssembly::MUL_v4i32, WebAssembly::MUL_v4i32_S },
  { WebAssembly::MUL_v8i16, WebAssembly::MUL_v8i16_S },
  { WebAssembly::NARROW_S_v16i8, WebAssembly::NARROW_S_v16i8_S },
  { WebAssembly::NARROW_S_v8i16, WebAssembly::NARROW_S_v8i16_S },
  { WebAssembly::NARROW_U_v16i8, WebAssembly::NARROW_U_v16i8_S },
  { WebAssembly::NARROW_U_v8i16, WebAssembly::NARROW_U_v8i16_S },
  { WebAssembly::NEAREST_F32, WebAssembly::NEAREST_F32_S },
  { WebAssembly::NEAREST_F64, WebAssembly::NEAREST_F64_S },
  { WebAssembly::NEG_F32, WebAssembly::NEG_F32_S },
  { WebAssembly::NEG_F64, WebAssembly::NEG_F64_S },
  { WebAssembly::NEG_v16i8, WebAssembly::NEG_v16i8_S },
  { WebAssembly::NEG_v2f64, WebAssembly::NEG_v2f64_S },
  { WebAssembly::NEG_v2i64, WebAssembly::NEG_v2i64_S },
  { WebAssembly::NEG_v4f32, WebAssembly::NEG_v4f32_S },
  { WebAssembly::NEG_v4i32, WebAssembly::NEG_v4i32_S },
  { WebAssembly::NEG_v8i16, WebAssembly::NEG_v8i16_S },
  { WebAssembly::NE_F32, WebAssembly::NE_F32_S },
  { WebAssembly::NE_F64, WebAssembly::NE_F64_S },
  { WebAssembly::NE_I32, WebAssembly::NE_I32_S },
  { WebAssembly::NE_I64, WebAssembly::NE_I64_S },
  { WebAssembly::NE_v16i8, WebAssembly::NE_v16i8_S },
  { WebAssembly::NE_v2f64, WebAssembly::NE_v2f64_S },
  { WebAssembly::NE_v4f32, WebAssembly::NE_v4f32_S },
  { WebAssembly::NE_v4i32, WebAssembly::NE_v4i32_S },
  { WebAssembly::NE_v8i16, WebAssembly::NE_v8i16_S },
  { WebAssembly::NOP, WebAssembly::NOP_S },
  { WebAssembly::NOT_v16i8, WebAssembly::NOT_v16i8_S },
  { WebAssembly::NOT_v2i64, WebAssembly::NOT_v2i64_S },
  { WebAssembly::NOT_v4i32, WebAssembly::NOT_v4i32_S },
  { WebAssembly::NOT_v8i16, WebAssembly::NOT_v8i16_S },
  { WebAssembly::OR_I32, WebAssembly::OR_I32_S },
  { WebAssembly::OR_I64, WebAssembly::OR_I64_S },
  { WebAssembly::OR_v16i8, WebAssembly::OR_v16i8_S },
  { WebAssembly::OR_v2i64, WebAssembly::OR_v2i64_S },
  { WebAssembly::OR_v4i32, WebAssembly::OR_v4i32_S },
  { WebAssembly::OR_v8i16, WebAssembly::OR_v8i16_S },
  { WebAssembly::PCALL_INDIRECT_VOID, WebAssembly::PCALL_INDIRECT_VOID_S },
  { WebAssembly::PCALL_INDIRECT_exnref, WebAssembly::PCALL_INDIRECT_exnref_S },
  { WebAssembly::PCALL_INDIRECT_f32, WebAssembly::PCALL_INDIRECT_f32_S },
  { WebAssembly::PCALL_INDIRECT_f64, WebAssembly::PCALL_INDIRECT_f64_S },
  { WebAssembly::PCALL_INDIRECT_i32, WebAssembly::PCALL_INDIRECT_i32_S },
  { WebAssembly::PCALL_INDIRECT_i64, WebAssembly::PCALL_INDIRECT_i64_S },
  { WebAssembly::PCALL_INDIRECT_v16i8, WebAssembly::PCALL_INDIRECT_v16i8_S },
  { WebAssembly::PCALL_INDIRECT_v2f64, WebAssembly::PCALL_INDIRECT_v2f64_S },
  { WebAssembly::PCALL_INDIRECT_v2i64, WebAssembly::PCALL_INDIRECT_v2i64_S },
  { WebAssembly::PCALL_INDIRECT_v4f32, WebAssembly::PCALL_INDIRECT_v4f32_S },
  { WebAssembly::PCALL_INDIRECT_v4i32, WebAssembly::PCALL_INDIRECT_v4i32_S },
  { WebAssembly::PCALL_INDIRECT_v8i16, WebAssembly::PCALL_INDIRECT_v8i16_S },
  { WebAssembly::POPCNT_I32, WebAssembly::POPCNT_I32_S },
  { WebAssembly::POPCNT_I64, WebAssembly::POPCNT_I64_S },
  { WebAssembly::PRET_CALL_INDIRECT, WebAssembly::PRET_CALL_INDIRECT_S },
  { WebAssembly::QFMA_v2f64, WebAssembly::QFMA_v2f64_S },
  { WebAssembly::QFMA_v4f32, WebAssembly::QFMA_v4f32_S },
  { WebAssembly::QFMS_v2f64, WebAssembly::QFMS_v2f64_S },
  { WebAssembly::QFMS_v4f32, WebAssembly::QFMS_v4f32_S },
  { WebAssembly::REM_S_I32, WebAssembly::REM_S_I32_S },
  { WebAssembly::REM_S_I64, WebAssembly::REM_S_I64_S },
  { WebAssembly::REM_U_I32, WebAssembly::REM_U_I32_S },
  { WebAssembly::REM_U_I64, WebAssembly::REM_U_I64_S },
  { WebAssembly::REPLACE_LANE_v16i8, WebAssembly::REPLACE_LANE_v16i8_S },
  { WebAssembly::REPLACE_LANE_v2f64, WebAssembly::REPLACE_LANE_v2f64_S },
  { WebAssembly::REPLACE_LANE_v2i64, WebAssembly::REPLACE_LANE_v2i64_S },
  { WebAssembly::REPLACE_LANE_v4f32, WebAssembly::REPLACE_LANE_v4f32_S },
  { WebAssembly::REPLACE_LANE_v4i32, WebAssembly::REPLACE_LANE_v4i32_S },
  { WebAssembly::REPLACE_LANE_v8i16, WebAssembly::REPLACE_LANE_v8i16_S },
  { WebAssembly::RETHROW, WebAssembly::RETHROW_S },
  { WebAssembly::RETURN, WebAssembly::RETURN_S },
  { WebAssembly::RET_CALL, WebAssembly::RET_CALL_S },
  { WebAssembly::RET_CALL_INDIRECT, WebAssembly::RET_CALL_INDIRECT_S },
  { WebAssembly::ROTL_I32, WebAssembly::ROTL_I32_S },
  { WebAssembly::ROTL_I64, WebAssembly::ROTL_I64_S },
  { WebAssembly::ROTR_I32, WebAssembly::ROTR_I32_S },
  { WebAssembly::ROTR_I64, WebAssembly::ROTR_I64_S },
  { WebAssembly::SELECT_EXNREF, WebAssembly::SELECT_EXNREF_S },
  { WebAssembly::SELECT_F32, WebAssembly::SELECT_F32_S },
  { WebAssembly::SELECT_F64, WebAssembly::SELECT_F64_S },
  { WebAssembly::SELECT_I32, WebAssembly::SELECT_I32_S },
  { WebAssembly::SELECT_I64, WebAssembly::SELECT_I64_S },
  { WebAssembly::SHL_I32, WebAssembly::SHL_I32_S },
  { WebAssembly::SHL_I64, WebAssembly::SHL_I64_S },
  { WebAssembly::SHL_v16i8, WebAssembly::SHL_v16i8_S },
  { WebAssembly::SHL_v2i64, WebAssembly::SHL_v2i64_S },
  { WebAssembly::SHL_v4i32, WebAssembly::SHL_v4i32_S },
  { WebAssembly::SHL_v8i16, WebAssembly::SHL_v8i16_S },
  { WebAssembly::SHR_S_I32, WebAssembly::SHR_S_I32_S },
  { WebAssembly::SHR_S_I64, WebAssembly::SHR_S_I64_S },
  { WebAssembly::SHR_S_v16i8, WebAssembly::SHR_S_v16i8_S },
  { WebAssembly::SHR_S_v2i64, WebAssembly::SHR_S_v2i64_S },
  { WebAssembly::SHR_S_v4i32, WebAssembly::SHR_S_v4i32_S },
  { WebAssembly::SHR_S_v8i16, WebAssembly::SHR_S_v8i16_S },
  { WebAssembly::SHR_U_I32, WebAssembly::SHR_U_I32_S },
  { WebAssembly::SHR_U_I64, WebAssembly::SHR_U_I64_S },
  { WebAssembly::SHR_U_v16i8, WebAssembly::SHR_U_v16i8_S },
  { WebAssembly::SHR_U_v2i64, WebAssembly::SHR_U_v2i64_S },
  { WebAssembly::SHR_U_v4i32, WebAssembly::SHR_U_v4i32_S },
  { WebAssembly::SHR_U_v8i16, WebAssembly::SHR_U_v8i16_S },
  { WebAssembly::SHUFFLE, WebAssembly::SHUFFLE_S },
  { WebAssembly::SPLAT_v16i8, WebAssembly::SPLAT_v16i8_S },
  { WebAssembly::SPLAT_v2f64, WebAssembly::SPLAT_v2f64_S },
  { WebAssembly::SPLAT_v2i64, WebAssembly::SPLAT_v2i64_S },
  { WebAssembly::SPLAT_v4f32, WebAssembly::SPLAT_v4f32_S },
  { WebAssembly::SPLAT_v4i32, WebAssembly::SPLAT_v4i32_S },
  { WebAssembly::SPLAT_v8i16, WebAssembly::SPLAT_v8i16_S },
  { WebAssembly::SQRT_F32, WebAssembly::SQRT_F32_S },
  { WebAssembly::SQRT_F64, WebAssembly::SQRT_F64_S },
  { WebAssembly::SQRT_v2f64, WebAssembly::SQRT_v2f64_S },
  { WebAssembly::SQRT_v4f32, WebAssembly::SQRT_v4f32_S },
  { WebAssembly::STORE16_I32, WebAssembly::STORE16_I32_S },
  { WebAssembly::STORE16_I64, WebAssembly::STORE16_I64_S },
  { WebAssembly::STORE32_I64, WebAssembly::STORE32_I64_S },
  { WebAssembly::STORE8_I32, WebAssembly::STORE8_I32_S },
  { WebAssembly::STORE8_I64, WebAssembly::STORE8_I64_S },
  { WebAssembly::STORE_F32, WebAssembly::STORE_F32_S },
  { WebAssembly::STORE_F64, WebAssembly::STORE_F64_S },
  { WebAssembly::STORE_I32, WebAssembly::STORE_I32_S },
  { WebAssembly::STORE_I64, WebAssembly::STORE_I64_S },
  { WebAssembly::STORE_V128, WebAssembly::STORE_V128_S },
  { WebAssembly::SUB_F32, WebAssembly::SUB_F32_S },
  { WebAssembly::SUB_F64, WebAssembly::SUB_F64_S },
  { WebAssembly::SUB_I32, WebAssembly::SUB_I32_S },
  { WebAssembly::SUB_I64, WebAssembly::SUB_I64_S },
  { WebAssembly::SUB_SAT_S_v16i8, WebAssembly::SUB_SAT_S_v16i8_S },
  { WebAssembly::SUB_SAT_S_v8i16, WebAssembly::SUB_SAT_S_v8i16_S },
  { WebAssembly::SUB_SAT_U_v16i8, WebAssembly::SUB_SAT_U_v16i8_S },
  { WebAssembly::SUB_SAT_U_v8i16, WebAssembly::SUB_SAT_U_v8i16_S },
  { WebAssembly::SUB_v16i8, WebAssembly::SUB_v16i8_S },
  { WebAssembly::SUB_v2f64, WebAssembly::SUB_v2f64_S },
  { WebAssembly::SUB_v2i64, WebAssembly::SUB_v2i64_S },
  { WebAssembly::SUB_v4f32, WebAssembly::SUB_v4f32_S },
  { WebAssembly::SUB_v4i32, WebAssembly::SUB_v4i32_S },
  { WebAssembly::SUB_v8i16, WebAssembly::SUB_v8i16_S },
  { WebAssembly::SWIZZLE, WebAssembly::SWIZZLE_S },
  { WebAssembly::TEE_EXNREF, WebAssembly::TEE_EXNREF_S },
  { WebAssembly::TEE_F32, WebAssembly::TEE_F32_S },
  { WebAssembly::TEE_F64, WebAssembly::TEE_F64_S },
  { WebAssembly::TEE_I32, WebAssembly::TEE_I32_S },
  { WebAssembly::TEE_I64, WebAssembly::TEE_I64_S },
  { WebAssembly::TEE_V128, WebAssembly::TEE_V128_S },
  { WebAssembly::THROW, WebAssembly::THROW_S },
  { WebAssembly::TRUNC_F32, WebAssembly::TRUNC_F32_S },
  { WebAssembly::TRUNC_F64, WebAssembly::TRUNC_F64_S },
  { WebAssembly::TRY, WebAssembly::TRY_S },
  { WebAssembly::UNREACHABLE, WebAssembly::UNREACHABLE_S },
  { WebAssembly::XOR_I32, WebAssembly::XOR_I32_S },
  { WebAssembly::XOR_I64, WebAssembly::XOR_I64_S },
  { WebAssembly::XOR_v16i8, WebAssembly::XOR_v16i8_S },
  { WebAssembly::XOR_v2i64, WebAssembly::XOR_v2i64_S },
  { WebAssembly::XOR_v4i32, WebAssembly::XOR_v4i32_S },
  { WebAssembly::XOR_v8i16, WebAssembly::XOR_v8i16_S },
  { WebAssembly::fp_to_sint_v2i64_v2f64, WebAssembly::fp_to_sint_v2i64_v2f64_S },
  { WebAssembly::fp_to_sint_v4i32_v4f32, WebAssembly::fp_to_sint_v4i32_v4f32_S },
  { WebAssembly::fp_to_uint_v2i64_v2f64, WebAssembly::fp_to_uint_v2i64_v2f64_S },
  { WebAssembly::fp_to_uint_v4i32_v4f32, WebAssembly::fp_to_uint_v4i32_v4f32_S },
  { WebAssembly::int_wasm_widen_high_signed_v4i32_v8i16, WebAssembly::int_wasm_widen_high_signed_v4i32_v8i16_S },
  { WebAssembly::int_wasm_widen_high_signed_v8i16_v16i8, WebAssembly::int_wasm_widen_high_signed_v8i16_v16i8_S },
  { WebAssembly::int_wasm_widen_high_unsigned_v4i32_v8i16, WebAssembly::int_wasm_widen_high_unsigned_v4i32_v8i16_S },
  { WebAssembly::int_wasm_widen_high_unsigned_v8i16_v16i8, WebAssembly::int_wasm_widen_high_unsigned_v8i16_v16i8_S },
  { WebAssembly::int_wasm_widen_low_signed_v4i32_v8i16, WebAssembly::int_wasm_widen_low_signed_v4i32_v8i16_S },
  { WebAssembly::int_wasm_widen_low_signed_v8i16_v16i8, WebAssembly::int_wasm_widen_low_signed_v8i16_v16i8_S },
  { WebAssembly::int_wasm_widen_low_unsigned_v4i32_v8i16, WebAssembly::int_wasm_widen_low_unsigned_v4i32_v8i16_S },
  { WebAssembly::int_wasm_widen_low_unsigned_v8i16_v16i8, WebAssembly::int_wasm_widen_low_unsigned_v8i16_v16i8_S },
  { WebAssembly::sint_to_fp_v2f64_v2i64, WebAssembly::sint_to_fp_v2f64_v2i64_S },
  { WebAssembly::sint_to_fp_v4f32_v4i32, WebAssembly::sint_to_fp_v4f32_v4i32_S },
  { WebAssembly::uint_to_fp_v2f64_v2i64, WebAssembly::uint_to_fp_v2f64_v2i64_S },
  { WebAssembly::uint_to_fp_v4f32_v4i32, WebAssembly::uint_to_fp_v4f32_v4i32_S },
}; // End of getStackOpcodeTable

  unsigned mid;
  unsigned start = 0;
  unsigned end = 571;
  while (start < end) {
    mid = start + (end - start)/2;
    if (Opcode == getStackOpcodeTable[mid][0]) {
      break;
    }
    if (Opcode < getStackOpcodeTable[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return getStackOpcodeTable[mid][1];
}

} // end namespace WebAssembly
} // end namespace llvm
#endif // GET_INSTRMAP_INFO